Dual damascence process utilizing teos-based silicon oxide...

Details Dual damascence process utilizing teos-based silicon oxide... Dual damascence process utilizing teos-based silicon oxide...

2008-05-27

2008-05-27

Pham, Thanhha (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S624000, C438S700000, C257SE21579

Reexamination Certificate

active

07378343

ABSTRACT:
A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

REFERENCES:
patent: 2006/0154086 (2006-07-01), Fuller et al.

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