Dual CPU on-chip-debug low-gate-count architecture with...

Details Dual CPU on-chip-debug low-gate-count architecture with... Dual CPU on-chip-debug low-gate-count architecture with...

2005-12-15

2008-10-14

Iqbal, Nadeem (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

Reexamination Certificate

active

07437616

ABSTRACT:
The same microcontroller chip is configured to be either a Target version or a Link version of a microcontroller. The Target version runs an application program. To debug the Target microcontroller, the Link version of the microcontroller functions as a master debug microcontroller to the slave Target microcontroller running the application program. The Link microcontroller runs an interface translator program between a Host computer that runs a debug program, and the Target microcontroller. The Link microcontroller communicates with the Target microcontroller using a fast, 2-wire interface. The Link microcontroller communicates with the Host computer through a general purpose interface.

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