Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-06-30
2010-12-14
Lohn, Joshua (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C710S240000, C711S118000
Reexamination Certificate
active
07853824
ABSTRACT:
The present invention is to provide a computer for backup and being fault-tolerant comprising a CPU connected to an I/O port, a dual-port memory, a memory address decoder, a bus tri-state buffer, and an arbitration circuit, where the CPU can access data of the dual-port memory based on a decoded memory address of the memory address decoder, first and second ports of the dual-port memory are connected to input and output of the bus tri-state buffer respectively, and an output of the arbitration circuit is connected to an enable terminal of the bus tri-state buffer. Thus, when two identical computers are connected together as a dual computer system, both computers can perform the same operations, compare and change operation data each other via the I/O port and the dual-port memory, and control an output value of the arbitration circuit based on the comparison results for causing the bus tri-state buffer to enter a bi-directional communication state or a high impedance disconnected state, forcing either malfunctioned computer to surrender its control of the system bus.
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Bacon & Thomas PLLC
DMP Electronics Inc.
Lohn Joshua
Truong Loan L. T.
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