Multiplex communications – Channel assignment techniques – Arbitration for access to a channel
Reexamination Certificate
1998-05-29
2001-07-03
Ton, Dang (Department: 2732)
Multiplex communications
Channel assignment techniques
Arbitration for access to a channel
Reexamination Certificate
active
06256320
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to clocks for a network, and in particular to methods and systems for multiple clocks for ports on a hub.
2. Description of Related Art
Computer networks are called upon to handle increasingly higher speeds of data transmission. Computer networks often involve numerous end stations coupled together in a hub for communication with each other. Such hubs may represent a bottleneck for efficiency in transmission between the various end stations or other elements of the network. A hub often includes a number of ports, which are coupled to the end stations or other devices in the computer network. Ports are then coupled to other ports via a bus within the hub. Some hubs used in computer networks are repeating hubs and others are switching hubs.
Within the hub, ports must transmit and receive onto the common bus. Conflicts may occur when the various ports attempt to simultaneously transmit from the same bus. One system for resolving conflicts between entities sharing a common transmission medium is the carrier sensed multiple access with collision detect (CSMA-CD) scheme. Under such a scheme, entities attempting to transmit over the shared medium attempt to transmit over the medium and if a conflict occurs then the entities do not transmit at that time. Such a scheme may involve inefficiencies in the use of the transmission medium. More efficient and robust systems for sharing media such as a bus within a hub are needed.
As computer networks increase in speed, components within network devices may be called upon to operate at higher speeds. Clocks for controlling operation of such high speed components are important. However, physical limitations of a bus may prevent the bus from running at a desired clock speed.
SUMMARY
An embodiment of the invention includes a hub including at least a port, the port having an internal data path having a first width; a bus coupled to the port, the bus having a data path having a second width, wherein the second width is greater than the first width; a first clock having a first frequency, the first clock coupled to circuitry in the port for clocking internal data transfers; and a second clock having a second frequency less than the first frequency, the second clock coupled to circuitry in the port for clocking data transfers with the bus.
According to an aspect of the invention, the second clock comprises the first clock divided. According to another embodiment of the invention, the second clock is phase locked with the first clock. According to an embodiment of the invention, a ratio between the first width and the second width corresponds to a ratio between the second frequency and the first frequency.
According to another embodiment of the invention, a ratio between the first width and the second width equals a ratio between the second frequency and the first frequency. According to one embodiment of the invention, the first width comprises 16 bits and the second width comprises 32 bits. Alternatively, the second width comprises a number in the range of 32 to 128 bits. The first frequency may comprise about 63 MHz and the second frequency about 31 MHz. According to an aspect of the invention, data has a delay from transmission on the bus to receipt at a port of less than a period of the second clock.
According to an aspect of the invention, the second clock has a state during which data transfers with the bus are clocked, the state beginning at a time sufficiently long enough after data is clocked from a source to allow the data to be stable at the port at a leading edge of the first clock during the state. According to another aspect of the invention, the second clock has a state during which data transfers with the bus are clocked, a delay exists from data being clocked from a source to data being received at the port, and the delay is sufficient to allow the data to be stable at the port at leading edge of the first clock during the state. The first clock or second clock or both clocks are coupled other than via the bus to the circuitry in the port for clocking internal data transfers.
An embodiment of the invention includes a full duplex Ethernet hub comprising a plurality of ports coupled to a shared backplane bus, a clock coupled to a port in the plurality of ports, the first clock having a first frequency, a second clock coupled to the port, the second clock having a second frequency, the second frequency lower than the first frequency, and logic to clock data into the port based on a state of the first clock and a state of the second clock.
An aspect of the invention is directed to a method of transferring data in a network device having a bus and at least a circuit coupled to the bus. The method comprises clocking data within the circuit with a first signal having a first frequency, the first signal provided other than via the bus; and clocking data into the circuit with a second signal having a second frequency, the second signal provided other than via the bus. According to one aspect, the data is clocked into the circuit with the first signal and the second signal. According to another aspect, the data is clocked into the circuit with the second leading edge of the first signal after a leading edge of the first signal at which the data was clocked out of a source.
The invention includes a distributed arbitration scheme for an internal bus network device. Ports in a network device determine which port in a set of ports may broadcast a packet onto a bus in the network device. An embodiment of the invention is a method of transmitting data between a set of ports sharing a bus in hub. The set of ports includes a first port, and the method comprises the first port receiving a packet, the first port requesting the bus, and, if another port is requesting the bus, the first port transmitting the packet to the bus if the first port has not transmitted a packet later than the another port requesting the bus.
According to an aspect of the invention, the first port transmits based on port numbers of respective ports requesting the bus. According to another aspect of the invention, the first port does not transmit if another port requesting the bus has a lower port number. According to another aspect of the invention, the first port transmits based on whether a buffer coupled to another port is full.
According to various embodiments of the invention, the hub comprises a fiber module or the hub comprises a 100 base SX module.
An embodiment of the invention includes a method of transmitting data between a set of ports sharing a bus in an Ethernet hub. The set of ports including a first port. The first port enters a first state if the first port has received the packet and the first port wins an arbitration with other ports requesting the bus. The packet is transmitted after the first port has entered the first state. The port exits the first state, and after exiting the first state, enters a wait state and remains in the wait state until no other port is requesting the bus.
An aspect of the invention includes entering a second wait state if the first port does not win the arbitration. A further aspect of the invention includes exiting the second wait state after a particular time interval.
An embodiment of the invention includes an Ethernet hub. The hub includes a plurality of ports coupled to a bus. Respective ports have logic that, if a port has received a packet and the port has not transmitted a packet during the current cycle, causes the port to request the bus and transmit the packet if the port wins an arbitration with other ports in the plurality of ports requesting the bus. According to an aspect of the invention, the current cycle ends when no port is requesting the bus.
According to an aspect of the invention a plurality of buffers is coupled to respective ports, and the hub includes logic to cause the port to not transmit the packet if a buffer among the respective buffers is full.
According to an aspect of the invention, the hub includes respective lines coupl
Tang Wen-Tsung
Wadhawan Ruchi
3Com Corporation
McDonnell & Boehnen Hulbert & Berghoff
Sam Phirin
Ton Dang
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