Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Patent
1998-11-27
2000-03-07
Auve, Glenn A.
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
36523003, G06F 1300
Patent
active
060353651
ABSTRACT:
A synchronous memory device having at least one memory section which includes a plurality of memory cells. The memory device comprises a register to store a value which is representative of a delay time after which the memory device responds to a read request and clock receiver circuitry to receive first and second external clock signals. The memory device also includes an output driver(s) to output data on a bus, in response to a read request and in accordance with the delay time, wherein a first portion of the data is output synchronously with respect to the first external clock signal and a second portion of the data is output synchronously with respect to the second external clock signal. The memory device may include a delay locked loop to generate internal clock signal(s) using the external clock signal(s). The output drivers output data on the bus in response to the internal clock signal(s). The memory device may include input receiver circuitry, coupled to the bus, the receive the read request, wherein the read request is sampled from the bus synchronously with respect to the first external clock signal.
REFERENCES:
patent: 4099231 (1978-07-01), Kotok et al.
patent: 4183095 (1980-01-01), Ward
patent: 4247817 (1981-01-01), Heller
patent: 4337523 (1982-06-01), Hotta et al.
patent: 4360870 (1982-11-01), McVey
patent: 4445204 (1984-04-01), Nishiguchi
patent: 4519034 (1985-05-01), Smith et al.
patent: 4570220 (1986-02-01), Tetrick et al.
patent: 4734880 (1988-03-01), Collins
patent: 4740923 (1988-04-01), Kaneko et al.
patent: 4792926 (1988-12-01), Roberts
patent: 4802127 (1989-01-01), Akaogi et al.
patent: 4821226 (1989-04-01), Christopher et al.
patent: 4845664 (1989-07-01), Aichelmann, Jr. et al.
patent: 4882712 (1989-11-01), Ohno et al.
patent: 4916670 (1990-04-01), Suzuki et al.
patent: 4928265 (1990-05-01), Beighe et al.
patent: 4951251 (1990-08-01), Yamaguchi et al.
patent: 4953128 (1990-08-01), Kawai et al.
patent: 4953130 (1990-08-01), Houston
patent: 4970418 (1990-11-01), Masterson
patent: 4975872 (1990-12-01), Zaiki
patent: 5016226 (1991-05-01), Hiwada et al.
patent: 5018111 (1991-05-01), Madland
patent: 5040153 (1991-08-01), Fung et al.
patent: 5056064 (1991-10-01), Iwahashi et al.
patent: 5075886 (1991-12-01), Isobe et al.
patent: 5077693 (1991-12-01), Hardee et al.
patent: 5083296 (1992-01-01), Hara et al.
patent: 5107465 (1992-04-01), Fung et al.
patent: 5140688 (1992-08-01), White et al.
patent: 5153856 (1992-10-01), Takahashi
patent: 5175835 (1992-12-01), Beighe et al.
patent: 5200926 (1993-04-01), Iwahashi et al.
patent: 5206833 (1993-04-01), Lee
patent: 5251309 (1993-10-01), Kinoshita et al.
patent: 5301278 (1994-04-01), Bowater et al.
patent: 5361277 (1994-11-01), Grover
patent: 5390149 (1995-02-01), Vogley et al.
patent: 5841580 (1998-11-01), Farmwald et al.
patent: 5841707 (1998-11-01), Cline et al.
E.H. Frank "The SBUS: Sun's High Performance System Bus for RISC Workstations" Sun Microsystems Inc. 1990.
H. L. Kalter et al."A 50-ns 16Mb DRAM with a 10-ns Data Rate and On-Chip ECC" IEEE Journal of Solid State Circuits, vol. 25 No. 5, pp. 1118-1128 (Oct. 1990).
J. Chun et al. "A pipelined 650MHz GaAs 8K ROM with Translation Logic" GaAs IC Symposium 1990.
T.L. Jeremiah et al., "Synchronous Packet Switching Memory And I/O Channel," IBM Tech. Disc. Bul,. vol. 24, No. 10, pp. 4986-4987 (Mar. 1982).
L. R. Metzeger, "A 16K CMOS PROM with Polysilicon Fusible Links", IEEE Journal of Solid State Circuits, vol. 18 No. 5, pp. 562-567 (Oct. 1983).
A. Yuen et. al., "A 32K ASIC Synchronous RAM Using a Two-Transistor Basic Cell", IEEE Journal of Solid State Circuits, vol. 24 No. 1, pp. 57-61 (Feb. 1989).
D.T. Wong et. al., "An 11-ns 8Kx18 CMOS Static RAM with 0.5-.mu.m Devices", IEEE Journal of Solid State Circuits, vol. 23 No. 5, pp. 1095-1103 (Oct. 1988).
T. Williams et. al., "An Experimental 1-Mbit CMOS SRAM with Configurable Organization and Operation", IEEE Journal of Solid State Circuits, vol. 23 No. 5, pp. 1085-1094 (Oct. 1988).
D. Jones, "Synchronous static ram", Electronics and Wireless World, vol. 93, No. 1622, pp. 1243-4 (Dec. 1987).
F. Miller et. al., "High Frequency System Operation Using Synchronous SRAMS", Midcon/87 Conference Record, pp. 430-432 Chicago, IL, USA; Sep. 15-17, 1987.
K. Ohta, "A 1-Mbit DRAM with 33-MHz Serial I/O Ports", IEEE Journal of Solid State Circuits, vol. 21 No. 5, pp. 649-654 (Oct. 1986).
K. Nogami et. al., "A 9-ns HIT-Delay 32-kbyte Cache Macro for High-Speed RISC", IEEE Journal of Solid State Circuits, vol. 25 No. 1, pp. 100-108 (Feb. 1990).
F. Towler et. al., "A 128k 6.5ns Access/ 5ns Cycle CMOS ECL Static RAM", 1989 IEEE international Solid State Circuits Conference, (Feb. 1989).
M. Kimoto, "A 1.4ns/64kb RAM with 85ps/3680 Logic Gate Array", 1989 IEEE Custom Integrated Circuits Conference.
D. Wendell et. al. "A 3.5ns, 2Kx9 Self Timed SRAM", 1990 IEEE Symposium on VLSI Circuits (Feb. 1990).
M. Bazes et. al., "A Programmable NMOS DRAM Controller for Microcomputer Systems with Dual-Port Memory and Error Checking and Correction", IEEE Journal of Solid State Circuits, vol. 18 No. 2, pp. 164-172 (Apr. 1983).
R. Schmidt, "A memory Control Chip fo Formatting Data into Blocks Suitable for Video Applications", IEEE Transactions on Circuits and Systems, vol. 36, No. 10 (Oct. 1989).
D. K. Morgan "The CVAX CMCTL--A CMOS Memory Controller Chip", Digital Technical Journal, No. 7 (Aug. 1988).
T.C. Poon et. al., "A CMOS DRAM-Controller Chip Implementation", IEEE Journal of Solid State Circuits, vol. 22 No. 3, pp. 491-494 (Jun. 1987).
Farmwald Michael
Horowitz Mark
Auve Glenn A.
Rambus Inc.
Steinberg Neil
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