Dual clock domain deskew circuit

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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Details

C327S153000, C327S158000, C327S161000

Reexamination Certificate

active

07656983

ABSTRACT:
In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.

REFERENCES:
patent: 2006/0188050 (2006-08-01), Jenkins et al.
patent: 2006/0261869 (2006-11-01), Gomm et al.

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