Dual chip package

Details Dual chip package Dual chip package

2007-02-01

2008-11-18

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S185050, C365S185070, C365S230060

Reexamination Certificate

active

07453713

ABSTRACT:
The present invention is directed to a dual chip package that is connected to a host and includes a first memory chip and a second memory chip. Each of the first and second memory chips includes a flash memory; an option pad connected to either a first or second voltage; a register configured to store a flag signal indicating whether a memory chip is selected; a comparator circuit configured to compare a flag signal stored in the register with a logic value apparent at the option pad to generate a flash access signal. Each of the first and second memory chips also includes a memory controller unit configured to access the flash memory in response to the flash access signal, and an interrupt controller unit configured to provide an interrupt signal to the host in response to the flash access signal and a control signal provided from the host.

REFERENCES:
patent: 5303180 (1994-04-01), McAdams
patent: 5768173 (1998-06-01), Seo et al.
patent: 6889268 (2005-05-01), Chae et al.
patent: 6991964 (2006-01-01), Matsuo et al.
patent: 2005/0141318 (2005-06-01), Lee
patent: 2002-133884 (2002-05-01), None
patent: 2004-039211 (2004-02-01), None
patent: 2005-196739 (2005-07-01), None
patent: 1020040003558 (2004-01-01), None
patent: 1020050067784 (2005-07-01), None

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