Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2002-11-07
2004-06-22
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S064000, C257S686000, C257S777000
Reexamination Certificate
active
06753206
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit (IC) packages, and more particularly, to a dual-chip integrated circuit package with unaligned chip arrangement and a method of manufacturing such a dual-chip integrated circuit package.
2. Description of Related Art
A DIP (Dual In-Line Package) is a type of integrated circuit package that includes a metal leadframe with a die pad and a plurality of leads. An integrated circuit chip is mounted on the die pad and electrically connected via a set of conductive wires to the leads, and an encapsulant is formed to encapsulate the entire integrated circuit chip, the entire die pad, and part of the lead fingers therein so as to allow easy handling and utilization of the integrated circuit package and to protect the enclosed integrated circuit chip from being contaminated or damaged by outside objects.
In the design and manufacture, it is usually desired to mount as many integrated circuit chips in a single integrated circuit package as possible so as to allow one single integrated circuit package to offer more functions. An integrated circuit package that packs two integrated circuit chips therein is customarily referred to as a dual-chip integrated circuit package. Since a dual-chip integrated circuit package packs two integrated circuit chips rather than just one, it can help save layout space on the circuit board and offers more functionality and storage capacity. A conventional dual-chip integrated circuit package is disclosed in U.S. Pat. No. 5,012,323, whose structure is briefly described in the following with reference to
FIGS. 8-10
.
As shown in
FIG. 8
, the U.S. Pat. No. 5,012,323 utilizes a dual-row lead-frame
21
which includes a left part and a right part (as delimited by the dashed line
25
). The left part includes a set of left-outer leads
23
LO and a set of left-inner leads
23
LI, while the right part includes a set of right-outer leads
23
RO and a set of right-inner leads
23
RI. Further, the left part is formed with a left slot
26
L between the left-outer leads
23
LO and the left-inner leads
23
LI (as the area enclosed in the dashed box), while the right part is formed with a right slot
26
R between the right-outer leads
23
RO and the right-inner leads
23
RI (as the area enclosed in the dashed box). The dual-chip integrated circuit package is used to pack two integrated circuit chips therein, including an upper die
41
and a lower die
43
, as shown in
FIGS. 9 and 10
. The lower die
43
has its top side attached by means of an insulative adhesive layer
44
on the bottom side of the left-inner leads
23
LI and the right-inner leads
23
RI, while the upper die
41
has its back side attached by means of another insulative adhesive layer
42
on the upper side of the left-inner leads
23
LI and the right-inner leads
23
RI. As illustrated in
FIGS. 9 and 10
, the lower die
43
should be greater in size than the upper die
41
so as to allow the left side
43
L and the right side
43
R of the lower die
43
to extend respectively into the left slot
26
L and the right slot
26
R; and the length from the left side
41
L to the right side
41
R of the upper die
41
should be less than the distance between the left slot
26
L and the right slot
26
R so as to facilitate the wire-bonding process for electrically connecting the bonding pads
43
LP and
43
RP via the bonding wires
47
to the left-outer leads
23
LO, the left-inner leads
23
LI, the right-outer leads
23
RO, and the right-inner leads
23
RI. In a similar manner, the bonding pads
41
LP,
41
RP on the left side
41
L and the right side
41
R of the upper die
41
are electrically connected via the bonding wires
47
to the left-outer leads
23
LO, the left-inner leads
23
LI, the right-outer leads
23
RO, and the right-inner leads
23
RI. An encapsulant
24
is then molded to enclose the upper die
41
, the lower die
43
, the left-outer leads
23
LO, the left-inner leads
23
LI, the right-outer leads
23
RO, and the right-inner leads
23
RI.
The foregoing patent allows two integrated circuit chips of different purposes, for example a microprocessor chip and a memory chip, to be packed in the same integrated circuit package. Moreover, since each integrated circuit chip is attached on the leads of the leadframe, it can help reduce the jointed area between the integrated circuit chip and the leads; and as a result, delamination between the integrated circuit chip and the leads can be prevented under temperature change conditions. One drawback to the forgoing patent, however, is that the lower die
43
should be greater in size than the upper die
41
(see
FIGS. 9 and 10
) so as to allow the left side
43
L and the right side
43
R of the lower die
43
to extend into the left slot
26
L and the right slot
26
R for the purpose of positioning the bonding pads
43
LP and
43
RP in the left slot
26
L and the right slot
26
R to facilitate the wire-bonding process. For this reason, the foregoing patent is only suitable for use in TYPE II integrated circuit packages, which is the type whose outer leads are arranged on the longer sides of the integrated circuit package, and is unsuitable for use in TYPE I integrated circuit packages, which is the type whose outer leads are arranged on the shorter sides of the integrated circuit package. The flash memory chip is typically and suitably encapsulated a TYPE I integrated circuit package. Therefore, the fore-going patent cannot be used to pack two integrated circuit chips of which at least one is a flash memory chip to provide a doubled storage capacity from a single integrated circuit package. Still one more drawback to the foregoing patent is that the jointed area between each integrated circuit chip and the leads of the leadframe is still considered large.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a dual-chip integrated circuit package and a method of manufacturing the same, which can be used to pack two integrated circuit chips of various relative sizes.
It is another objective of this invention to provide a dual-chip integrated circuit package and a method of manufacturing the same, which is suitable for use to pack flash memory chips.
It is still another objective of this invention to provide a dual-chip integrated circuit package and a method of manufacturing the same, which can be manufactured through the use of conventional equipment and processes without having to use new ones.
In accordance with the foregoing and other objectives, the invention proposes a new dual-chip integrated circuit package and a method of manufacturing the same.
The dual-chip integrated circuit package of the invention includes the following constituent parts: (a) a leadframe having a first set of leads and a second set of leads, the first and second sets of leads being each defined into an inner part and an outer part, with a spacing being defined between the inner part of the first set of leads and the inner part of the second set of leads; (b) a first integrated circuit chip having a first side where at least one row of bonding pads are formed and a second side insulatively attached to a first side of the inner part of the first set of leads; (c) a second integrated circuit chip having a first side where at least one row of bonding pads are formed, with part of the first side being insulatively attached to a second side of the inner part of the first set of leads in such a manner as to allow the bonding pads on the second integrated circuit chip to be positioned in the spacing; (d) a first set of bonding wires for electrically connecting the bonding pads on the first integrated circuit chip to selected part of the leads; (e) a second set of bonding wires for electrically connecting the bonding pads on the second integrated circuit chip to selected part of the leads; and (f) an encapsulant for encapsulating the first integrated circuit chip, the second integrated circuit chip, the first set of bonding wires, the second set of bond
Chang Michael
Chiang Lian-Cherng
Huang Chien-Ping
Cao Phat X.
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Siliconware Precision Industries Co. Ltd.
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