Dual chip in package with a wire bonded die mounted to a...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

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C257S723000, C257S777000, C257S668000, C257S685000, C257S786000, C257S784000, C257S737000, C257S738000, C257S692000, C257S693000, C257S778000, C257S700000, C257S701000, C257S783000

Reexamination Certificate

active

06586825

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to semiconductor packaging. More specifically, the invention relates to the design and manufacturing process of a semiconductor package that allows the incorporation of more than one chip device into a single package.
BACKGROUND OF THE INVENTION
For a variety of reasons well known in the art, semiconductor packages that have more than one chip, otherwise known as multi-chip modules (“MCM's”), are becoming increasingly popular. One type of MCM is shown in FIG.
1
. The MCM shown in
FIG. 1
comprises a top die
10
stacked on top of a bottom die
12
, which is in turn mounted on a substrate
18
. Bond pads (not shown) on the top die
10
and the bottom die
12
serve to interface the signal/power/ground outputs of the top and bottom dies
10
and
12
to an external device. Specifically, to electrically connect bond pads on the top die
10
to the substrate
18
, a first plurality of wires
14
run from the top die to the bottom die
12
, and a second plurality of wires
16
, some of which are electrically coupled to the first plurality of wires
14
, run from the bottom die to the substrate
18
. The remainder of the second plurality of wires couple the first semiconductor die's own signal/power/ground outputs to the substrate
18
.
From the top surface of the substrate
18
, signals are routed through a plurality of vias such as via
22
and/or along layers within the substrate
18
and thence to a plurality of solder balls
20
on the bottom surface of the substrate
18
.
The plurality of solder balls
20
are in turn connected to an external circuit board (not shown), thereby connecting the signal/power/ground outputs from the top and bottom semiconductor dies
10
and
12
to the external circuit board.
The MCM shown in
FIG. 1
has at least one significant drawback. In particular, the bottom die
12
must be larger than the top die
10
to accommodate the first plurality of wires
14
(and the corresponding plurality of bond pads on the bottom die
12
). Thus, two dies that are equal in size (i.e. surface area of relevant surfaces), or whose sizes differ by no more than a certain amount, may not be stacked in an MCM such as the one shown in FIG.
1
. (With current die sizes known to the inventors hereof, the bottom die
12
must be at least 2 mm longer than the top die
10
along each of the four edges of the dies
10
and
12
such that the bottom die
12
must have a surface area at least 4 mm×4 mm, or 16 mm
2
, greater than the top die.) This is a significant constraint since it is often desirable to stack two similarly sized dies in an MCM.
A designer of a package such as that shown in
FIG. 1
who desires to stack dies that would otherwise be similarly sized has to increase the size of one of them such that the sizes differ by no more than the maximum allowable size difference. Larger die sizes result in larger package sizes, which is undesirable. Further, larger die sizes mean that the number of dies per semiconductor wafer is lower, which increases manufacturing costs.
One possible scheme for stacking two die in a package is disclosed in U.S. patent application Ser. No. 09/467,543 is entitled “Dual Chip in Package,” filed Dec. 10, 1999, and is owned by the assignee of the present invention. According to this scheme, a top die and a bottom die are separated by an interposer. The bottom die is mounted flip-chip style on a substrate while the top die is wire bonded to the substrate. Unlike the package shown in
FIG. 1
, since the bottom die is flip chip mounted to the substrate, it does not have any bond wires that must be accommodated, thereby avoiding the, problems associated with the package shown in FIG.
1
. Although the package shown in the '543 application is effective, it is often desirable to have a bottom die that is wire bonded to the substrate.
Therefore, there is a need for an MCM package with a bottom die that is wire bonded to a substrate and a top die that is approximately the same size as the bottom die.
SUMMARY OF THE INVENTION
To achieve the foregoing, the present invention provides an apparatus and method for manufacturing a multi-chip module that comprises two similarly or identically sized dies. Although the present invention meets the above mentioned need pertaining to similarly or identically sized dies, the present invention may also have utility in cases where the dies have substantially different sizes.
According to one embodiment of the present invention, a package comprises two similarly size dies, a top die and a bottom die. The top die has top and bottom surfaces and the bottom die has top and bottom surfaces. The bottom die is mounted on a substrate, which has a top surface, such that the bottom surface of the bottom die faces the top surface of the substrate. Preferably, a thermally conductive adhesive is disposed between the bottom surface of the bottom die and the top surface of the substrate. The top die and bottom die are electrically connected to the substrate by wires. In turn, the substrate comprises a plurality of solder balls that electrically connect the substrate, and therefore the top die and bottom die, with an external device.
The bottom surface of the top die is separated from the top surface of the bottom die by an interposer. Thus, the interposer creates a space between the exterior regions of the top surface of the bottom die and the bottom surface of the top die. The wires that are electrically connected to the bottom die run through this space (i.e. run between the top surface of the bottom die and the bottom surface of the top die). Allowing these wires to run underneath the top die enables the top die to be at least as large as the bottom die.


REFERENCES:
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patent: 6362518 (2002-03-01), Yatsuda
patent: 6400019 (2002-06-01), Hirashima et al.
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patent: 2001/0029666 (2001-10-01), Nakamura et al.
patent: 2002/0030263 (2002-03-01), Akram
patent: 2002/0056897 (2002-05-01), Yatsuda
patent: 2002/0096746 (2002-07-01), Cokely et al.
patent: 8-255980 (1996-10-01), None

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