Dual chien search blocks in an error-correcting decoder

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Reexamination Certificate

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06920600

ABSTRACT:
A decoder and decoding method are described, in which a syndrome is calculated from a codeword in a syndrome generator, an error polynomial is generated based upon the syndrome in an error polynomial generator, an error location is determined from the error polynomial in the error location generator, an error magnitude is calculated from the error polynomial in the error magnitude generator and the codeword is corrected by a error corrected codeword generator responsive to location and error magnitude. An intra-decoder block messaging scheme is described in which one or more components generate inactivity messages to signal an ability to process data corresponding to a next codeword. A dual Chien search block implementation is described in which Chien block is used to determine the number of errors corresponding to a specified codeword, separately from error location and magnitude calculations performed by the Chien/Forney block. An enhanced Chien search cell architecture is described which utilizes an additional Galois field adder to synchronize the codeword and error vector, thereby decreasing delay and expense corresponding to an error correcting block implemented with a LIFO register.

REFERENCES:
patent: 3983536 (1976-09-01), Telfer
patent: 4364081 (1982-12-01), Hashimoto et al.
patent: 4567594 (1986-01-01), Deodhar
patent: 4586183 (1986-04-01), Wilkinson
patent: 4649541 (1987-03-01), Lahmeyer
patent: 4875211 (1989-10-01), Murai et al.
patent: 5099482 (1992-03-01), Cameron
patent: 5107503 (1992-04-01), Riggle et al.
patent: 5373511 (1994-12-01), Veksler
patent: 5414719 (1995-05-01), Iwaki et al.
patent: 6058500 (2000-05-01), DesJardins et al.
patent: 6061826 (2000-05-01), Thirumoorthy et al.
patent: 6065149 (2000-05-01), Yamanaka
patent: 6092233 (2000-07-01), Yang
patent: 6131178 (2000-10-01), Fujita et al.
patent: 6175945 (2001-01-01), Okita
patent: 6192497 (2001-02-01), Yang et al.
patent: 6195781 (2001-02-01), Kosuge
“Quantum Reed—Solomon Codes”, Markus Grassl, Willi Geiselmann, and Thomas Beth, Institut für Algorithmen und Kognitive Systeme, Arbeitsgruppe Quantum Computing, Universität Karlsruhe, Am Fasanengarten 5, 76 128 Karlsruhe, Germany, pp. 1-14.
“Optimal Finite Field Multipliers for FPGAs”, Captain Gregory C. Ahlquist, Brent Nelson, and Michael Rice, article found at http://splish.ee.byu.edu/docs/ffmult.fp199.pdf—Similiar pages, Mar. 1, 2001, 10 pages.
“Tutorial on Reed-Solomon Error Correction Coding”, William A. Geisel, NASA Technical Memorandum 102162, Aug. 1990, pp. 72-74.
“Error Control Systems for Digital Communication and Storage”, Stephen B. Wicker, Library of Congress Cataloging-in-Publication Data, p. 209.
“Parallel Decoder for Cellular Automata Based Byte Error Correcting Code”, S. Chattopadhyay and P. Pal Chaudhuri, 10th International Conference on VLSI Design, Jan. 1997, pp. 527-528.
“Designing a Reed-Solomon Codec in an ADSL System using a C6201 DSP”, by Han Kuo, article found, at http://www.csdmag.com
ews/des0111011.htm, Mar. 9, 2001, 10 pages.
“A Faster Way To Run Reed Solomon Decoders”, Torjell Berg and Aaron Brennan, American Microsystems Inc., Article found at http://www.eetasia.com/article_content.php3?article id=8800067078 Mar. 9, 2001; posted: Jan. 1, 2001, 3 pages.
“XF-RSDEC Reed Solomon Decoder”, article found at http://www.xilinx.com/products/logicore/alliance/memec/xf rsdec.pdf; Jan. 10, 2000, pp. 3-1-3-5.
“Reed-Solomon Codes—‘An introduction to Reed-Solomon codes: principles, architecture and implementation’”, article found at http://www.4i2i.com/reed solomon codes.htm, Mar. 9, 2001, 8 pages.

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