Dual cache RAM for rapid invalidation

Details Dual cache RAM for rapid invalidation Dual cache RAM for rapid invalidation

1988-08-29

1990-05-29

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

365 49, 364200, G11C 1500

Patent

active

049301063

ABSTRACT:
A cache buffer for a multiprocessor system utilizes two RAMs to store validity bits. Use of these RAMs greatly reduces chip area required to implement the validity buffer and reduces interconnection foil (printed connectors) and hence propagation time. An initial clear state is written into all of the memory locations of both RAMs. One of the RAMs then becomes the active validity bit RAM and the other a standby. When a fast invalidate command is received, upon an invalidate parity error indication from a memory readout, for example, the standby RAM is switched to the active RAM, and the validity bits of the formerly active RAM are cleared in sequential write cycles after it is switched to a standby state.

REFERENCES:
patent: 3845474 (1974-10-01), Lange et al.
patent: 4825412 (1989-04-01), Sager et al.

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