Dual bus memory burst architecture

Details Dual bus memory burst architecture Dual bus memory burst architecture

2005-07-12

2005-07-12

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

C365S189020, C365S189050, C365S189120, C365S230030, C365S230040

Reexamination Certificate

active

06917545

ABSTRACT:
A method and apparatus for a memory device including a burst architecture employs a double bus architecture that is multiplexed onto an output bus at clock rate that is doubled. The resulting architecture effectively doubles throughput without increasing memory device latency.

REFERENCES:
patent: 5732406 (1998-03-01), Bassett
patent: 6202120 (2001-03-01), Lang
patent: 6243309 (2001-06-01), Shin
patent: 6580637 (2003-06-01), Pascucci

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