Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-03
2003-03-11
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S349000
Reexamination Certificate
active
06531741
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to silicon on insulator (SOI) integrated circuits, and more particularly to an SOI structure in which the thickness of the buried insulating film varies to change the thermal and capacitive coupling to the substrate wafer.
BACKGROUND OF THE INVENTION
Integrated circuits continue to be developed at a very rapid pace and higher density, higher speed and larger capacity devices continue to be achieved. Particularly, it has been recognized that by forming semiconductor devices using an SOI structure, increased performance and packaging density can be obtained. An SOI structure has semiconductor devices formed on a substrate in which a buried insulator region is typically formed by ion implantation. A known SOI structure is shown in
FIG. 1. A
buried oxide film
3
is arranged between first
1
and second
2
substrates. As shown in the figure, the buried oxide film
3
is of uniform thickness and both the top
4
and bottom
5
surfaces of the buried oxide
3
are substantially planar. It is known to form various circuit elements in the second substrate, for example, a MOSFET as shown in FIG.
1
. Source and drain regions
7
,
8
are formed in the second substrate
2
. A gate structure
9
is then formed over the second substrate
2
between the source and drain regions
7
,
8
. The buried oxide film
3
insulates the first substrate
1
commonly referred to as the bulk substrate, from the second substrate
2
, the body of the transistor.
SOI provides significant advantages over bulk technology and will achieve the scaling objectives of low power and high performance for future technologies. SOI provides reduced short channel effects, reduced electric field strength, reduction of parasitic capacitance, higher speed and lower power consumption, among other technology benefits.
However, the buried insulator introduces a thermal impedance in series with the bulk substrate. This thermal impedance can be detrimental to temperature control or self heating of SOI device structures, for example the resistors, capacitors, MOSFETs, diodes or other device structures which may be contained in an SOI process. Reducing the thermal resistance in series with the SOI structure can provide advantages regarding device operation, failure mechanism and reliability, for example, hot E, electromigration, and electrostatic discharge (ESD) protection among others. Additionally, the capacitive coupling with the bulk substrate is affected by the thickness of the buried insulator. These thermal and capacitive effects can either be detrimental or advantageous, depending on the circuit device.
Thus, there is a need for an SOI structure which can reduce the thermal impedance, the thermal capacitance, and the capacitive coupling effects where desired in the semiconductor device, while at the same time utilizing these effects in areas where they are beneficial.
SUMMARY OF THE INVENTION
A method and apparatus thereof for forming a dual thickness buried oxide SOI structure is provided. The present invention varies the thickness of the buried oxide to alter the thermal resistance, the thermal capacitance and the electrical capacitance in certain areas of semiconductor devices used in an SOI process. The present invention allows the thickness of the buried oxide to be varied over an entire silicon wafer, in an individual circuit element, or in both. The present invention can thus provide reduced or increased thermal resistance, thermal capacitance and electrical capacitance wherever desired in a particular implementation.
According to one embodiment of the invention, a first substrate layer having raised portions each with a planar top surface is provided. A dielectric layer is formed over the first substrate layer and its raised portions. The dielectric layer has a planar top surface. A second substrate layer is arranged on the planar top surface of the dielectric layer.
In another embodiment, a first substrate layer having raised portions is provided. A first non-continuous dielectric layer is provided on top of the first substrate layer. The top surface of the first dielectric layer is substantially co-planar with the top surfaces of the raised portions of the first substrate. A second continuous dielectric layer is formed over the first dielectric layer and the raised portions of the first substrate. The second dielectric layer has a planar top surface. A second substrate is formed on top of the planar top surface of the second dielectric layer.
Various methods can be used to realize the dual thickness buried oxide structure of the present invention. According to one method, a first blanket layer of oxygen ions is implanted to a predetermined depth in a substrate. A mask is then formed on the substrate and a second oxygen ion implantation takes place. The second masked oxygen ion implant is done deeper than, but forms a region continuous with the first oxygen ion implant. The mask is then removed and the ion implanted substrate is heat treated to form a buried oxide layer.
In another method, an oxide growth retarding implant region is formed in a selected area of a substrate. A blanket oxygen ion implant is then performed over the entire substrate. The oxygen ion implant is done at an energy level and a dose such that it reaches at least to the oxide growth retarding region. The oxide growth retarding implant prevents the oxide layer from forming in selected areas of the substrate resulting in a dual thickness buried oxide. The substrate is then heat treated to form the dual thickness buried oxide layer.
According to another method, shallow trench isolation is performed in the substrate. The substrate is then polished and a oxide layer with a co-planar top surface is formed on top thereof in a known manner. A second substrate wafer is then attached on the co-planar top surface of the oxide layer and heat treatment is performed for bonding. The second substrate layer is then etched to a desired thickness.
REFERENCES:
patent: 4704302 (1987-11-01), Bruel et al.
patent: 5608252 (1997-03-01), Nakato
patent: 6143591 (2000-11-01), Manning
Hargrove Michael J.
Voldman Steven H.
Chadurjian M. F.
Connolly Bove & Lodge & Hutz LLP
Dickey Thomas L.
International Business Machines - Corporation
Tran Minh Loan
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