Static information storage and retrieval – Read/write circuit – Having bipolar circuit element
Reexamination Certificate
2003-09-22
2004-06-29
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having bipolar circuit element
C365S104000, C365S177000, C257S406000, C257S405000, C438S287000
Reexamination Certificate
active
06757208
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile (NVM) device. More particularly, it relates to a dual-bit nitride read only memory (NROM) cell with parasitic amplifier and methods of fabricating and reading the same.
2. Description of the Related Art
In the nonvolatile memory (NVM) industry, the development of nitride read-only memory (NROM) started in 1996. Newer non-volatile memory technology utilizes oxide-nitride-oxide (ONO) gate dielectric and known mechanisms of programming and erasing to create two separate bits per cell. Thus, the NROM bit size is half of the cell area. Since silicon die size is a main element of cost structuring, it is apparent why the NROM technology is considered an economic breakthrough.
FIG. 1
is a schematic cross-section of a conventional dual-bit nitride read only memory cell. The cell includes a substrate
10
and two doped regions
12
and
14
therein, having a conductive type opposite to the substrate
10
. On top of the substrate
10
lies an oxide-nitride-oxide (ONO) structure
22
having a layer of silicon nitride
18
sandwiched between two oxide layers
16
and
20
. On top of the ONO structure
22
lies a gate conductor
24
. Between doped regions
12
and
14
is a channel
26
formed under ONO structure
22
.
The silicon nitride layer
18
in the ONO structure
22
has two chargeable areas
28
and
30
adjacent to the doped regions
12
and
14
. These chargeable areas
28
and
30
are used for storing charges during memory cell programming. To program the left bit (not shown) close to area
28
, the left doped region
12
is the drain and receives a high programming voltage. Simultaneously, the right doped region
14
is the source and grounded. The opposite is true for programming area
30
. Moreover, each bit can be read in a direction opposite its programming direction. To read the left bit, stored in area
28
, left doped region
12
is the source and right doped region
14
is the drain. The opposite is true for reading the right bit, stored in area
30
. In addition, the bits can be erased in the same direction in which they are programmed.
Reading of the described NROM device can be achieved by conventional MOS transistor operations. When charges are present in the area
28
or
30
(i.e. the bit is programmed), the raised threshold of the device does not permit the device place to enter a conductive state during reading. If charges are not present, the read voltage on gate conductor
24
can overcome the much lower threshold and accordingly, channel
26
becomes inverted and hence conductive.
In U.S. Pat. No. 5,768,192, Eitan discloses an improved reading method of NROM cell, wherein the direction thereof is opposite to that of programming.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is to provide a novel dual-bit nitride read only memory cell having a parasitic current amplifier therein contributive to reading out the memory status of the bits therein.
Another object of the invention is to provide methods of fabricating and reading a dual-bit nitride read only memory cell with parasitic current amplifier, wherein the current amplifier can amplify leakage currents sensed therein into amplified currents. Thus, the memory status of a reading bit can be precisely read out through examination of the amplified currents.
Thus, the dual-bit nitride read only memory cell with parasitic amplifier in accordance with the present invention comprises a semiconductor substrate. A first well region is disposed in the substrate, having a conductive type opposite to the substrate. A second well region is disposed in the first well region having a conductive type opposite to the second well region. A gate dielectric layer is disposed over portions of the second well region, wherein the gate dielectric layer comprises a nitride layer. A conductive layer is disposed on the gate dielectric layer to form a gate. And, a pair of first doped regions are symmetrically disposed in the second well region on both sides of the gate, having a conductive type opposite to the second well region, wherein one of the first doped regions, the second well region, and the first well region constitute a parasitic current amplifier.
Furthermore, the method of fabricating the dual-bit nitride read only memory cell with parasitic amplifier in accordance with the present invention comprises providing a semiconductor substrate, forming a first well region in the substrate having a conductive type opposite to the substrate, forming a second well region having a conductive type opposite to the first well region in the first well region, sequentially forming a dielectric layer and a conductive layer over the portions of second well region to form a gate thereon, wherein the dielectric layer comprises a nitride layer, and symmetrically forming a pair of first doped regions having a conductive type opposite to the second well region in the second well region on both sides of the gate, wherein one of the first doped regions, the second well region and the first well region constitute a parasitic current amplifier.
Moreover, the method of reading the dual-bit nitride read only memory cell with parasitic amplifier in accordance with the present invention comprises selecting a reading bit of the dual-bit nitride read only memory cell, floating the gate and grounding one of the first doped region on the opposite side thereof, applying a first voltage to the other first doped region adjacent to the reading bit to generate leakage currents into the second well region, applying a second voltage to the first well region on the opposite side of the reading bit to turn on the current amplifier therein and amplify the leakage currents and measuring amplified currents from the first well region on the opposite side of the reading bit to acquire the memory status of the reading bit.
In the present invention, a novel structure of a dualbit nitride read only memory cell having parasitic amplifier is provided and the parasitic amplifier formed by a BJT therein acts as a current amplifier during reading of the memory status of bits therein.
In addition, reading of the memory status of the bits is achieved by examination of the gate-induced drain leakages (GIDL) caused by the stored charges therein. The GIDL currents can be further amplified by the parasitic amplifier to generate amplified currents and memory status of the bits can be thus ascertained by the level of the amplified currents.
REFERENCES:
patent: 5578967 (1996-11-01), Harvey
patent: 6233168 (2001-05-01), Kokubun et al.
Huang Chiu-Tsung
Hung Chih-Wei
Birch & Stewart Kolasch & Birch, LLP
Powerchip Semiconductor Corp.
Tran Andrew Q.
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