Dual beam symmetric height systems and methods

Details Dual beam symmetric height systems and methods Dual beam symmetric height systems and methods

2001-10-09

2003-07-22

Pyo, Kevin (Department: 2878)

Radiant energy

Photocells; circuits and apparatus

With circuit for evaluating a web, strand, strip, or sheet

C250S559290, C356S237200

Reexamination Certificate

active

06597006

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to systems and methods for determining a height of a specimen. Certain embodiments relate to systems and methods that may include a dual beam symmetric height sensor coupled to a processing tool, a metrology tool, or an inspection tool.
2. Description of the Relevant Art
Fabricating semiconductor devices such as logic and memory devices may typically include processing a specimen such as a semiconductor wafer using a number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that typically involves transferring a pattern to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes may include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a semiconductor wafer and then separated into individual semiconductor devices.
As feature sizes of semiconductor devices continue to shrink, minimum feature sizes that may be successfully fabricated may often be limited by performance characteristics of semiconductor fabrication processes such as lithography and etch processes. Examples of performance characteristics of a lithography process include, but are not limited to, resolution capability, across chip linewidth variations, and across wafer linewidth variations. In optical lithography, such performance characteristics may be determined by a number of process parameters such as the quality of resist application, the performance of the resist, the exposure tool, and the wavelength of light which is used to expose the resist. The ability to resolve a minimum feature size, however, may also be strongly dependent on other critical parameters of lithography processes such as a temperature of a post exposure bake process or an exposure dose of an exposure process. As such, controlling the parameters of processes which are critical to the resolution capability of semiconductor fabrication processes such as lithography processes is becoming increasingly important to the successful fabrication of semiconductor devices.
Controlling critical process parameters may typically include assessing the performance characteristics of semiconductor fabrication processes such as resolution capability, across chip linewidth variations, and across wafer linewidth variations. As the dimensions of semiconductor devices continue to shrink with advances in semiconductor materials and processes, however, the ability to examine microscopic features and to detect microscopic defects in semiconductor devices has become increasingly difficult. Significant research has been focused on increasing resolution limits of metrology tools that are used to examine microscopic features and defects. Optical microscopes generally may have an inherent resolution limit of approximately 200 nm and may have limited usefulness in current manufacturing processes. Microscopes that utilize electron beams to examine devices, however, may be used to investigate feature sizes as small as, e.g., a few nanometers. Therefore, tools that utilize electron beams to inspect semiconductor devices are becoming integral to semiconductor fabrication processes. For example, in recent years, scanning electron microscopy has become increasingly popular for the inspection of semiconductor devices. Scanning electron microscopy typically involves scanning an electron beam over a specimen and generating an image of the specimen by detecting electrons that are reflected, scattered, or transmitted from the specimen.
During each semiconductor device fabrication process, defects such as particulate contamination and pattern defects may be introduced into the semiconductor devices. Such defects may be isolated to a single semiconductor device on a semiconductor wafer containing several hundred semiconductor devices. For example, isolated defects may be caused by random events such as an unexpected increase in particulate contamination in a manufacturing environment or an unexpected increase in contamination in process chemicals that may be used in fabrication of the semiconductor devices. Alternatively, the defects may be repeated in each semiconductor device formed across an entire semiconductor wafer. In an example, repeated defects may be systematically caused by contamination or defects on a reticle. A reticle, or a mask, may be disposed above a semiconductor wafer and may have substantially transparent regions and substantially opaque regions that are arranged in a pattern that may be transferred to a resist on the semiconductor wafer. Therefore, contamination or defects on a reticle may also be reproduced in the pattern transferred to the resist and may undesirably affect the features of each semiconductor device formed across an entire semiconductor wafer in subsequent processing.
Defects on semiconductor wafers may typically be monitored manually by visual inspection, particularly in the lithography process because many defects generated during a lithography process may be visible to the naked eye. Such defects may include macro defects that may be caused by faulty processes during this step. Defects that may be visible to the human eye typically have a lateral dimension greater than or equal to approximately 100 &mgr;m. Defects having a lateral dimension as small as approximately 10 &mgr;m, however, may also be visible on unpatterned regions of a semiconductor wafer. An example of a visual inspection method is illustrated in U.S. Pat. No. 5,096,291 to Scott and is incorporated by reference as if fully set forth herein. Prior to the commercial availability of automated defect inspection systems such as the systems illustrated in U.S. Pat. No. 5,917,588 to Addiego and U.S Pat. No. 6,020,957 to Rosengaus et al., which are incorporated by reference as if fully set forth herein, manual inspection was the most common, and may still be the most dominant, inspection method used by lithography engineers.
Automated inspection systems were developed to decrease the time required to inspect a wafer surface. Such inspection systems may typically include two major components such as an illumination system and a collection-detection system. An illumination system may include a light source such as a laser that may produce a beam of light and an apparatus for focusing and scanning the beam of light. Defects present on the surface may scatter the incident light. A detection system may detect the scattered light and may convert the detected light into electrical signals that may be measured, counted, and displayed on an oscilloscope or other monitor. Examples of such inspection systems are illustrated in U.S. Pat. No. 4,391,524 to Steigmeier et al., U.S. Pat. No. 4,441,124 to Heebner et al., U.S. Pat. No. 4,614,427 to Koizumi et al., U.S. Pat. No. 4,889,998 to Hayano et al., and U.S. Pat. No. 5,317,380 to Allemand, all of which are incorporated by reference as if fully set forth herein.
Systems used to manufacture semiconductor devices such as processing tools, metrology tools, and inspection tools may include a height sensor. A height sensor may be used to position a wafer within a system prior to the processing of the wafer. Height sensors may be used in different configurations for different applications. For example, height sensors may be used in wafer probe applications. Examples of such height sensors are illustrated in U.S. Pat. Nos. 4,328,553 to Fredriksen et al., and 5,948,972 to Samsavar et al., which are incorporated by reference as if fully set forth herein. In addition, height sensors may be used in wafer inspection applications. Examples of such height sensors are illustrated in U.S. Pat. Nos. 6,107,637 to Watanabe et al., 6,140,644 to Kawanami et al., and 6,172,365 to Hiroi et al., all of which are incorporated by reference as if fully set forth herein.
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