Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-05-10
2005-05-10
Beausoliel, Robert (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S013000, C713S002000
Reexamination Certificate
active
06892323
ABSTRACT:
A computer system has a central processing unit (CPU), and a chipset for supporting the CPU, and a selectable BIOS system. The chipset has a first general purpose input/output (GPIO) register. The selectable BIOS includes a primary and secondary BIOS programs, a timer circuit for generating a delay signal after power-on of the computer system, and a BIOS switching circuit. The primary BIOS program has confirmation code for generating a confirmation signal on the first GPIO register. The BIOS switching circuit shadows the primary or secondary BIOS program into a predetermined address space of the CPU according to the confirmation signal and the delay signal. While the primary BIOS program is shadowed, if the BIOS switching circuit receives the timer delay signal before receiving the BIOS confirmation signal, then the BIOS switching circuit causes the CPU to be reset and shadows the secondary BIOS program.
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Beausoliel Robert
Chu Gabriel L.
Giga-Byte Technology Co. Ltd.
Hsu Winston
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