Dual barrier and conductor deposition in a dual damascene proces

Details Dual barrier and conductor deposition in a dual damascene proces Dual barrier and conductor deposition in a dual damascene proces

1999-05-24

2000-11-14

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257750, 257915, H01L 2348

Patent

active

061474045

ABSTRACT:
An integrated circuit and a method for manufacturing therefor is provided in which a partial dual damascene deposition is performed to place a barrier, seed, and conductive layer in most of a via between two interconnect channels and then capping the via with a further barrier, seed, conductive layer to prevent electromigration between an interconnect channel and the via.

REFERENCES:
patent: 5592023 (1997-01-01), Oda
patent: 5686760 (1997-11-01), Miyakawa
patent: 5883433 (1999-03-01), Oda
patent: 6005291 (1999-12-01), Koyanagi et al.

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