Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-09-05
2001-05-29
Lee, Eddie C. (Department: 2815)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S626000, C438S622000, C438S584000, C438S643000, C438S634000, C438S628000, C257S751000, C257S750000, C257S915000, C257S752000, C257S763000, C257S764000
Reexamination Certificate
active
06239021
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to a dual damascene semiconductor and manufacturing method therefor.
BACKGROUND ART
In the process of manufacturing integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called “metalization”, and is performed using a number of different photolithographic and deposition techniques.
One metalization process, which is called the “damascene” technique starts with the placement of a first channel oxide (dielectric) layer, which is typically a silicon dioxide or oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The damascene step photoresist is stripped and a barrier layer is deposited to coat the walls of the first channel opening to ensure good adhesion and to act as a barrier material to prevent diffusion of a conductor (conductive material), such as copper, into the oxide layer and the semiconductor devices (the combination of the adhesion and barrier material is collectively referred to as “barrier layer” herein). A seed layer is then deposited on the barrier layer to form a conductive material base, or “seed”, for subsequent deposition of conductive material. The conductive material is then deposited in the first channel openings and subjected to a chemical-mechanical polishing process which removes the first conductive material above the first channel oxide layer and damascenes the conductive material in the first channel openings to form the first conductive channels.
For multiple layers of channels, another metalization process, which is called the “dual damascene” technique, is used in which the channels and vias are formed at the same time. In one example, the via formation step of the dual damascene technique starts with the deposition of a thin stop nitride over the first channels and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel oxide layer is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. A barrier layer is then deposited to coat the via openings and the second channel openings. Next, a seed layer is deposited on the barrier layer. This is followed by a deposition of the conductive material in the second channel openings and the via openings to form the second channel and the via. A second chemical-mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by a cylindrical via.
The use of the damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
One drawback of using copper is that barrier layers are required. Materials such as tantalum (Ta), titanium (Ti), and tungsten (W), their alloys, their nitrides, or combinations thereof are used as adhesion/barrier materials for copper. The barrier layers serve several different roles. First, they promote greater adhesion of the copper to the oxide layer. Second, they prevent diffusion of copper into the dielectric layer. And, third, they improve the resistance of copper to electromigration, which is the movement of copper atoms under the influence of current flow, which can cause voids in the copper.
The barrier layer improves the resistance to electromigration in two areas. First, along the length of a conductive channel in the direction of current flow where the barrier layer will be on three sides of the copper and the good interface reduces copper surface electromigration. And, second, in the contact area of a via with the conductive channel where the current density can be five times higher than in the conductive channel itself.
While the barrier layer between the via and the first conductive channel prevents electro-migration when the electron current flows from the second conductive channel through the via to the first conductive channel, when the electron current flows in the reverse direction, electro-migration occurs in the via as the copper migrates into the second conductive channel. This is a major problem since electro-migration causes voids to occur in the via which reduce the cross-sectional area of the via and increase electro-migration until there is an electrical failure between the first and second conductive channels.
Thus, a method for preventing electro-migration in the via, regardless of the direction of current flow, has long been sought but has eluded those skilled in the art. As the semiconductor industry moves from aluminum to copper and other types of materials with greater conductivity and thinner channels and narrower vias, it is becoming more pressing that an answer be found.
DISCLOSURE OF THE INVENTION
The present invention provides a semiconductor device having barrier layers on both top and bottom of conductive vias so as to eliminate electro-migration of conductive material under electron current flow between the top and bottom conductive channels.
The present invention provides a method for forming barrier layers on the top and bottom of conductive vias to prevent electro-migration of conductive materials under current flow from the bottom to top channels.
The present invention provides a semiconductor device having barrier layers on both top and bottom of conductive vias so as to eliminate electro-migration of copper under electron current flow between the top and bottom conductive channels.
The present invention provides a method for forming barrier layers on the top and bottom of conductive vias to prevent electro-migration of copper under electron current flow from the bottom to top channels.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
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Brown Dirk
Iacoponi John A.
Pramanick Shekhar
Advanced Micro Devices , Inc.
Brock II Paul E
Ishimaru Mikio
Lee Eddie C.
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