Dual bank queue memory and queue control system

Details Dual bank queue memory and queue control system Dual bank queue memory and queue control system

1997-12-05

2000-10-24

Patel, Ajit

Multiplex communications

Pathfinding or routing

Store and forward

370412, 370422, 710 52, H04L 1254

Patent

active

061378070

ABSTRACT:
An input processor recognizes and accepts a wide variety of protocols and formats. Queue management stores the uniform cells in a dual balanced bank memory system, which provides for utilizing an available bank of memory when the other bank of memory is in use, and otherwise balancing the use of the banks of memory, thereby maintaining equal free lists. Queue management apparatus and logic also ascertains and appends routing data to the stored data and transmits the data according to its priority.

REFERENCES:
patent: 5410540 (1995-04-01), Aiki et al.
patent: 5513174 (1996-04-01), Punj
patent: 5530698 (1996-06-01), Kozaki et al.
patent: 5535197 (1996-07-01), Cotton
patent: 5612952 (1997-03-01), Motoyama
patent: 5815501 (1998-09-01), Gaddis et al.
patent: 5825767 (1998-10-01), Mizukoshi et al.
patent: 5838677 (1998-11-01), Kozaki et al.

Affiliated with

Also associated with

Rating

Dual bank queue memory and queue control system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual bank queue memory and queue control system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual bank queue memory and queue control system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1972214