Dual bandwidth phase locked loop frequency lock detection...

Details Dual bandwidth phase locked loop frequency lock detection... Dual bandwidth phase locked loop frequency lock detection...

1997-08-04

2001-04-10

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S362000, C375S374000, C331S014000, C331S025000

Reexamination Certificate

active

06215834

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to a phase-locked loop (PLL) based clock generation system, and in particular to a frequency lock detector for a dual bandwidth PLL.
BACKGROUND OF THE INVENTION
When reacquiring phase-lock after being reenabled or at startup of the system, a PLL will overshoot the target frequency when initially attempting to acquire the programmed system frequency. If the PLL's targeted output frequency is at the maximum specified frequency of the system's processor, the PLL overshoot will cause memory access failures or execution failures in the processor. To prevent these problems, execution control circuitry produces a lock detect signal indicating when the PLL has locked to a programmed frequency, thereby indicating when the system can safely begin operation.
Historically, microprocessors and microcontrollers have utilized a PLL having dual bandwidth operation when the reference clock inputs are provided at low frequencies or for speeding up the locking process. A dual bandwidth PLL has two phases of operation: 1) a wide bandwidth (high gain) mode and 2) a narrow bandwidth (low gain) mode. Initially, the PLL is operated in wide bandwidth mode while a counter is used to count a delay period before the PLL is switched to the narrow bandwidth operation. Upon expiration of the delay, the PLL is transitioned into narrow bandwidth mode and the processor is released to begin execution of instructions. Thereafter, if the PLL has not acquired phase lock, the PLL transitions back to wide bandwidth mode and the counter is reinitiated. This process is repeated until the PLL has achieved phase lock. Unfortunately, if the system is operated at full frequency while acquiring phase lock, the overshoot of the PLL's output frequency of the PLL while operating in wide bandwidth mode can produce critical system failures. Therefore, it would be desirable to provide a system that will ensure that the PLL has fully settled prior to allowing the CPU to begin full speed operation and preventing such failures.


REFERENCES:
patent: 4477919 (1984-10-01), Borras et al.
patent: 4875108 (1989-10-01), Minuhin et al.
patent: 5254955 (1993-10-01), Saeki et al.
patent: 5394444 (1995-02-01), Silvey et al.
patent: 5661440 (1997-08-01), Osaka

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