Dual array read port functionality from a one port SRAM

Details Dual array read port functionality from a one port SRAM Dual array read port functionality from a one port SRAM

2005-03-15

2005-03-15

Aududuong, Gene N. (Department: 2818)

Static information storage and retrieval

Addressing

Multiple port access

C156S190000

Reexamination Certificate

active

06868033

ABSTRACT:
A storage cell includes a bit storage member capable of storing a data bit. The bit storage member includes a true data output, having a true data value corresponding to the data bit, and a complement data output, having a complement data value corresponding to a logical complement of the true data value. A first controllable gate is electronically coupled to the true data output and is responsive to a first read enable signal so that the true data value is passed through the first controllable gate when the first read enable signal is asserted. A second controllable gate is electronically coupled to the complement data output and is responsive to a second read enable signal so that the complement data value is passed through the second controllable gate when the second read enable signal is asserted.

REFERENCES:
patent: 4802122 (1989-01-01), Auvinen et al.
patent: 5644547 (1997-07-01), Grishakov et al.
patent: 6189068 (2001-02-01), Witt et al.
patent: 6272596 (2001-08-01), Nishimukai et al.

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