DSP memory bank rotation

Details DSP memory bank rotation DSP memory bank rotation

2005-05-17

2005-05-17

Elmore, Stephen (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S005000, C711S105000, C711S154000, C711S157000, C711S211000, C711S220000, C365S230030

Reexamination Certificate

active

06895488

ABSTRACT:
An apparatus comprising a memory, a plurality of modules, an address translation unit and a controller. The memory may be arranged as a plurality of memory banks. Each of the plurality of modules may be configured to generate one or more addresses for accessing a particular one of the plurality of memory banks. The address translation unit may be configured to modify the one or more addresses in response to a control signal. The controller may be configured to generate the control signal in response to a computer executable instruction.

REFERENCES:
patent: 4493027 (1985-01-01), Katz et al.
patent: 4633434 (1986-12-01), Scheuneman
patent: 4888687 (1989-12-01), Allison et al.
patent: 4894770 (1990-01-01), Ward et al.
patent: 4930066 (1990-05-01), Yokota
patent: 5269010 (1993-12-01), MacDonald
patent: 5835963 (1998-11-01), Yoshioka et al.
patent: 5924111 (1999-07-01), Huang et al.
patent: 6215719 (2001-04-01), Anraku
patent: 6289429 (2001-09-01), Okamoto
patent: 6356991 (2002-03-01), Bauman et al.
patent: 6381668 (2002-04-01), Lunteren
patent: 6553478 (2003-04-01), Grossier
patent: 20030140305 (2003-07-01), Gatherer et al.

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