Electrical computers and digital data processing systems: input/ – Interrupt processing
Patent
1998-04-17
2000-12-19
Etienne, Ario
Electrical computers and digital data processing systems: input/
Interrupt processing
710 48, 710263, 710269, G06F 1324
Patent
active
061638293
ABSTRACT:
A multi-processor system is provided having a processor array configured of a plurality of CPUs (20) that are disposed on a global bus (14). A VEM interface (18) is provided for interfacing between the global bus (14) and a system bus (12). Interrupts that are generated on the system bus (12) are mapped to the CPUs (20) through an interrupt controller (82). The interrupt controller (82) is operable to receive multiple interrupts and store these interrupts and their associated interrupt vectors. After storage, a gating register associated with each CPU (20) is examined to determine which interrupts are serviced by a particular CPU (20). If an interrupt is received that is to be serviced by one or more of the CPUs (20), then an external interrupt is generated for that CPU (20). Once the external interrupt is generated, the CPU will then examine a flag register associated therewith, which flag bits are set only if the interrupt controller (82) has determined that the CPU (20) is to receive the interrupt in accordance with the contents of the gating registers. The CPU (20) will then service the particular interrupts directed thereto by accessing the stored interrupt vectors. Once all CPUs (20) that are to service an interrupt have retrieved the interrupt vector, an acknowledgment signal is sent back to the system bus (12).
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Bartlett James R.
Greim Michael C.
Etienne Ario
Intelect Systems Corporation
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