Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
2000-08-14
2003-09-09
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C714S030000, C714S045000, C712S035000
Reexamination Certificate
active
06618775
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is in the field of development, debugging and testing tools for systems utilizing embedded processors.
2. Description of the Related Art
A broad selection of debugging tools traditionally have been available for the design and development of systems utilizing embedded microprocessors and microcontrollers. The use of these tools has been extended to the development of systems utilizing specialized processors such as reduced instruction set computers (RISC), co-processors and digital signal processors (DSP). Processor development tools have included hardware-oriented devices, such as in-circuit emulators and logic analyzers, and software-oriented devices, such as ROM monitors. Also included are on-chip debuggers, which fall somewhere between in-circuit emulators and ROM monitors.
A full-featured in-circuit emulator is the most powerful debugging tool. Connection between the emulator and the target system is accomplished with a pod that replaces the target system processor or fits on top of it. The emulator provides its own memory which overlays the target's RAM or ROM. Emulation allows single-step program execution, breakpoints, access to register and memory values, and the capture of program traces.
Logic analyzers are general purpose tools typically used to troubleshoot logic circuits, allowing the capture of logic state or timing traces upon the occurrence of a triggering event. While an emulator replaces the target system processor, a logic analyzer can be connected to a processor's external signals and used to passively monitor processor operation. Logic analyzers conventionally utilize probes which lock on and electrically attach to the microprocessor external pins. Unlike emulators, on-chip debuggers or ROM monitors, a logic analyzer requires no target resources. On the other hand, a logic analyzer only passively monitors the processor, and another tool is necessary for run control, memory and register reads and writes and code downloading.
A ROM monitor is essentially application code that resides in target ROM. Unlike an emulator, a ROM monitor runs on the target and needs significant target resources, such as an interrupt, a communication port and a RAM. A ROM monitor can provide run control, memory and register reads and writes and code downloading. On-chip debuggers are tools which take advantage of the on-chip debugging features found in some processors. A processor's on-chip debugging features are accessed through one or more dedicated pins. These features are typically debug registers implemented on the processor or special debug registers reserved for use by an on-chip debugger. Higher-level debugging features are provided by host-based debugger packages. These debugger packages can be used for single-stepping and setting breakpoints, reading and writing registers and memory, code downloading and resetting the processor.
Today's fast, complex processors make it harder to debug embedded systems using these traditional tools. To begin with, modem processors which incorporate superscalar program execution, on-chip program and data caches and multiple address and data buses have logic states that cannot be easily determined by accessing external device pins.
FIG. 1
is a block diagram of a prior art digital signal processor (DSP) illustrating a complex architecture with multiple internal buses, including a program address bus (PAB)
110
, a program read data bus (PRDB)
120
, a data write address bus (DWAB)
130
, a data write data bus (DWEB)
140
, a data read address bus (DRAB)
150
, and a data read data bus (DRDB)
160
.
FIG. 2
is a block diagram of another prior art DSP also illustrating a complex architecture with multiple internal buses, including a data memory address (DMA) bus
210
, a data memory data (DMD) bus
220
, a program memory address (PMA) bus
230
, and a program memory data (PMD) bus
240
.
Performance improvements in modem processors, such as increased clock rates and internal clock multiplication, also make debugging these embedded systems more difficult. The high frequency signals of many modem processors cannot tolerate the. capacitance associated with pod or probe assemblies and their associated cabling. Further, modem packaging techniques utilized to accommodate higher frequencies, such as surface mount devices, are not amenable to probe attachment. In addition, real-time circuits cannot be halted or slowed without altering the results.
Current debugging techniques are greatly restricted. Modern processors typically provide only a few dedicated serial pins through which registers can be initially set, processor execution started and registers can be examined. However, this greatly restricts the ability to monitor the internal processor states, hampering the development process. There is a need to provide non-invasive state monitoring capability on a processor chip to facilitate processor development.
SUMMARY OF THE INVENTION
A bus monitor is co-located with a processor on a chip or within a module. The bus monitor includes an interface, a bus watching circuit and a memory. The interface provides a connection between the external contacts of the chip or module package and the bus monitor. The interface has an input which allows trigger conditions to be downloaded from an external device to the bus monitor. The interface also has an output which allows a captured trace of bus states to be uploaded to an external device. The bus watching circuit monitors the data on at least one of the processor buses, producing a trigger output when a triggering event matches the downloaded trigger condition. The memory stores data from at least one of the processor buses in response to the bus watching circuit trigger output, creating a trace of states occurring on a bus. The memory also reads trace data from its storage to the interface output.
Another aspect of the current invention is a method of monitoring processor bus states occurring on at least one of a plurality of internal processor buses. The method involves downloading a trigger condition from an external device to the bus monitor. The downloaded trigger condition is compared with events occurring on monitored buses. In response to a comparison match, a trace of bus data is retained in storage. This trace data is then uploaded to an external device for analysis.
REFERENCES:
patent: 5142673 (1992-08-01), DeAngelis et al.
patent: 5210862 (1993-05-01), DeAngelis et al.
patent: 5313618 (1994-05-01), Pawloski
patent: 5325368 (1994-06-01), James et al.
patent: 5329471 (1994-07-01), Swoboda et al.
patent: 5355369 (1994-10-01), Greenberger et al.
patent: 5371551 (1994-12-01), Logan et al.
patent: 5375228 (1994-12-01), Leary et al.
patent: 5463760 (1995-10-01), Hamauchi
patent: 5488688 (1996-01-01), Gonzales et al.
patent: 5513338 (1996-04-01), Alexander et al.
patent: 5530804 (1996-06-01), Edgington et al.
patent: 5535412 (1996-07-01), Nadehara
patent: 5539901 (1996-07-01), Ramirez
patent: 5544311 (1996-08-01), Harenberg et al.
patent: 5546566 (1996-08-01), Katsuta
patent: 5560036 (1996-09-01), Yoshida
patent: 5561761 (1996-10-01), Hicok et al.
patent: 5566303 (1996-10-01), Tashiro et al.
patent: 5590354 (1996-12-01), Klapproth et al.
patent: 5610826 (1997-03-01), Whetsel
patent: 5621651 (1997-04-01), Swoboda
patent: 5623673 (1997-04-01), Gephardt et al.
patent: 5631910 (1997-05-01), Nozuyama et al.
patent: 5640542 (1997-06-01), Whitsel et al.
patent: 5671172 (1997-09-01), Britton
patent: 5729678 (1998-03-01), Hunt et al.
patent: 5812830 (1998-09-01), Naasch-Shahry et al.
patent: 5908392 (1999-06-01), Wilson et al.
patent: 5960457 (1999-09-01), Skrovan et al.
patent: 5999163 (1999-12-01), Ivers et al.
patent: 6026503 (2000-02-01), Gutgold et al.
Duane R. Aadsen, Harold N. Scholz, and Yervant Zorian;Automated Bist for Regular Structures Embedded in Asic Devices: AT&T Technical JournalMay/Jun. 1990; pp. 97-109.
D. Mukherjee, C. Njinda and M.A. Breuer,Synthesis of Optimal 1-Hot Coded On-Chip Controllers for
Gazdzinski & Associates
Micro)n Technology, Inc.
Ray Gopal C.
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