Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2001-04-03
2004-12-28
Lee, Thomas (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C370S505000, C370S516000
Reexamination Certificate
active
06836854
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
N/A
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
N/A
BACKGROUND OF THE INVENTION
In a synchronous network digital payload data is carried at a particular clock frequency within a synchronous message format. This payload data may include both asynchronous digital data and synchronous digital data originating at a different data rate in a foreign digital network. The Synchronous Optical Network (SONET) and its European counterpart the Synchronous Digital Hierarchy (SDH) provide a standard format of transporting digital signals having various data rates, such as a DS-0, DS-1, DS-1C, DS-2, or a DS-3 signal and their European counterparts within a Synchronous Payload Envelope (SPE), or a container that is a part of a SONET/SDH STS-N/STM-N message frame. In addition to the digital data that is mapped and framed within the SPE or container, the STS-N/STM-N message frame also includes overhead data that provides for coordination between various network elements.
If the digital data that is mapped and framed in the STS-N/STM-N message was originally carried by a clock signal having a different frequency than the SONET/SDH line rate clock, certain adjustments to the framed digital data must be made. For example, if a DS-3 data signal carried by a 44.763 MHz clock signal is to be carried in a fiber-optic network by mapping the DS-3 signal into the SPE of an STS-1 message, extra bits must be added to the DS-3 signal prior to transmission through the SONET/SDH network. These extra bits are commonly referred to as stuff bits or gap bits and are merely place markers and carry no valid data. These gap bits are required because the DS-3 signal is slower than the SONET/SDH clock frequency, and hence there are not enough DS-3 bits at the higher frequency to form a complete SONET frame.
When the STS-1 message is received at the exit node, the overhead bytes must be removed from the SONET STS-1 message. The payload data that remains is de-framed and de-mapped into a serial data stream carried by a higher clock frequency than the nominal clock frequency of the payload data. In addition, the recovered data still contains the inserted gap data bits. If, for example, DS-3 data has been transported via a SONET/SDH network, the DS-3 data must be converted from the SONET clock signal to the lower frequency DS-3 clock signal and the gap data bits must be removed prior to the DS-3 signal being B3ZS-encoded for electrical re-transmission.
To transfer data from one clock domain to another, for example from the DS-3 embedded within the SONET signal rate to the proper DS-3 signal rate, typically a desynchronizer is used to provide a buffering mechanism between the clock signals. A desynchronizer typically includes an elastic store buffer that can be a first-in-first-out memory that receives gapped data recovered from a synchronized data payload as an input at one clock frequency and stores the data in appropriate storage locations. Data is read from the elastic store buffer at a different clock frequency and is provided as output data at that frequency. This output data does not contain the gap data bits that were added when the slower signal was mapped into the faster SONET/SDH STS-1 message.
Once the data has been de-mapped and de-framed from the SPE and the gaps removed, a phase locked loop (PLL) is typically used to recover the clock information and to adjust the read signal associated with the data stored in the elastic store for transmission downstream of a smooth data clock signal carrying a smooth data signal.
Although the SONET/SDH fiber optic network is a synchronous network, variations in clock signals across the network may occur. These variations in clock signals between various network elements may cause a loss of data downstream from the sender if the clock signal at which data was written to the synchronous signal and the clock signal at which the data was read from the synchronous payload are sufficiently different. A variety of conditions can cause variations in clock signals. For example, network clock instability, electrical noise and interference, effective changes in the length of transmission media, changes in the velocity of propagation, Doppler shifts, and irregular timing information and other electrical and network problems may all cause clock variations.
To mitigate the problems caused by clock variations across a network, the SONET/SDH STS-N/STM-N messages are provided with a pointer adjustment mechanism within the transmission overhead bytes that allow for some movement of the data within the SPE. The pointer adjustment mechanism includes a pair of bytes, H
1
and H
2
, that identify the start of the next SONET/SDH payload byte and also indicate if the pointer adjustment byte, H
3
, is to be used. The third overhead byte, H
3
, provides for active pointer adjustment when a negative justification of the SPE is required. Positive justification involves marking the byte of after the H
3
byte as a dummy or stuff byte, or as valid data. These pointer adjustments, which occur in the H
1
and H
2
transmission overhead bytes, allow for up to eight (8) bits of data to be added to a SONET/SDH message frame (using the H
3
overhead byte) or for up to eight (8) bits to be removed from the frame. This allows for the SPE/container to be re-framed and re-synched at a network node that has a slightly different network clock. Thus, in addition to the gap data necessary to compensate for payload data that is carried by a different frequency clock signal, up to eight bits of data may be added or removed at each network element in the network due to clock instability in the network.
During a pointer adjustment, which may be also known as a pointer movement, the H
1
, H
2
, and H
3
bytes may either add or deplete eight (8) bits to/from the recovered data signal at one time. Pointer adjustments can be periodic or aperiodic in nature. A periodic pointer adjustment may be caused, for example, when the SPE transporting the data has a constant clock offset at the output node of the network relative to the input node. An aperiodic or non-periodic pointer adjustment may be bursty in nature when caused by a transient problem or condition within the network.
Although the synchronous system may adjust the payload data using pointer adjustments to account for clock and phase variations, the clock and phase shifts caused by the pointer adjustments and/or the de-gapping of the payload data can affect the output rate of the data clock provided by the PLL. Typically, clock and phase shifts have two components. One is a high frequency jitter component that is classified as a clock or phase shift that is greater than 10 Hz. A second is a low frequency wander component that is classified as a clock or phase shift that is less than 10 Hz.
Jitter refers to the phase variations in the clock signal, which may cause errors in identifying bit positions and values accurately, and is therefore an issue in synchronous systems. Wander refers to phase variations that typically affect the frame and time-slot synchronization. Each network element adds some amount of noise to the SPE that eventually contributes to the timing instability in the form of jitter and wander in the recovered payload signal.
As is known, the PLL used to recover the smooth clock signal and smooth data signal is able to smooth out some phase jumps caused by pointer adjustments or asynchronous stuff bits. A PLL is most effective at filtering out high frequency jitter components, i.e., those with a frequency greater than 10 Hz., but is not effective at filtering out the low frequency wander components. Since, typically the wander components are much less than 10 Hz. these wander components are well within the bandwidth of the PLL and are passed without being attenuated. To construct a PLL with a small enough bandwidth to filter the wander components of the phase jumps, large time constants in the PLL control loops would require large component values for the resistors and capacitors used in the PLL
Nakra Jahangir
Ranganath Balaji
Applied Micro Circuits Corporation
Chen Tse
Lee Thomas
Weingarten Schurgin, Gagnebin & Lebovici LLP
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