Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-11-30
2003-06-03
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06573175
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor device fabrication, and more particularly to methods of removing post-etch polymer and dielectric antireflective coatings without substantially etching the underlying dielectric layer, and solutions used in such methods.
BACKGROUND OF THE INVENTION
The continuing trend in the semiconductor industry toward densification of circuit devices has significantly improved performance of electronic devices that use integrated circuits. In a typical integrated circuit, individual circuit elements are electrically connected together by a metallization process in which layers of metal are deposited and patterned to form metal lines that complete the circuit as designed. Multiple metal layers are often employed. Metal lines within patterned metal layers are insulated by interlevel dielectric layers from undesired electrical contact both with other metal lines, whether in the same or another metal layer, and with other circuit elements.
In the construction of integrated circuit structures, dielectric materials such as silicon oxide (SiO
2
) have been conventionally used to electrically separate conductive elements of the integrated circuit structure. The increasing density of integrated circuits has resulted in unneeded capacitance between metal lines in an integrated circuit which slows circuit speed and can cause cross-coupling between adjacent conductive elements.
The use of insulation materials having lower dielectric constants (k values) than conventional silicon oxide (SiO
2
) have been described. One such class of material is a carbon doped silicon oxide material wherein at least a portion of the oxygen atoms bonded to the silicon atoms are replaced by one or more organic groups, for example, an alkyl group such as a methyl (CH
3
) group. Such low k carbon doped silicon oxide dielectric materials have dielectric constants varying from about 2.5 to about 3.5, and lowers the capacitance between conductive elements separated by such dielectric materials.
In connecting overlying layers of metal lines separated by a carbon-doped SiO
2
interlayer dielectric (ILD) layer, a photolithographic technique is used that typically employs a dielectric antireflective coating (DARC) layer and an overlying photoresist layer. High aspect ratio features such as vias/trenches that are etched through the ILD layer to an underlying metal line are subsequently cleaned to remove post-etch polymer and the DARC layer before depositing the metal fill. Current cleaning compositions etch a portion of the ILD layer during the cleaning step, which can have a negative impact on and significantly alter the critical dimensions of the etched feature.
Therefore, a need exists for a cleaning composition and process that overcomes such problems.
SUMMARY OF THE INVENTION
The present invention provides methods of selectively removing dielectric antireflective coatings (DARC) without substantially etching the underlying dielectric layer, for example, in the formation of conductive contacts in a semiconductor structure. The invention further provides compositions for the selective removal of post-etch polymer and a DARC layer. The method and composition help prevent degradation of the exposed surfaces of a low k carbon doped silicon oxide dielectric material during removal of post-etch polymer and antireflective coating after formation of vias or contact openings in the dielectric material.
In one aspect, the invention provides a method of cleaning a wafer surface. In one embodiment, the method comprises contacting a wafer substrate having overlying layers of a carbon-doped low k dielectric layer, a dielectric antireflective coating layer, and post-etch polymer material, with a cleaning solution to selectively remove the antireflective coating layer and the post-etch polymer, with substantially no etching of the low k dielectric layer. Preferably the etch rate ratio of the DARC layer to the low k dielectric layer is greater than 5:1, preferably greater than 10:1. In one embodiment, the cleaning composition comprises an effective amount of trimethylammonium fluoride (TMAF) to selective etch the ARC layer and post-etch polymer material. In another embodiment, the composition comprises effective amounts of TMAF and hydrogen fluoride (HF). In a further embodiment, effective amounts of TMAF and trimethylammonium hydroxide (TMAH) are combined to form the cleaning composition.
In another aspect, the invention provides a method of forming a conductive plug (via plug) and/or interconnect or contact. In one embodiment, the method includes providing a wafer comprising a substrate with an active area such as a metal line and overlying layers of low k dielectric layer, a dielectric antireflective coating (DARC) layer, and a photoresist layer; forming a opening through the low k dielectric layer to the active area on the substrate; and contacting the wafer with a cleaning solution to selectively remove the dielectric antireflective coating layer and post-etch polymer material with substantially no etching of the low k dielectric layer. A conductive metal can then be deposited to fill the opening (and/or trench) to form a conductive plug and a metal line (interconnect, contact). The method can be used to form single or dual damascene interconnects and via plugs in the manufacture of integrated circuits.
In yet another aspect, the invention provides a cleaning composition comprising one or more cleaning agents in amounts effective to selectively remove a dielectric antireflective coating (DARC) layer overlying a carbon-doped low k dielectric layer at an etch rate of the DARC layer to the low k dielectric layer that is greater than the etch rate ratio of the DARC material to TEOS. In one embodiment, the cleaning composition is formulated such that contact of the cleaning composition with a carbon-doped low k dielectric blanket layer for a time period of up to about 15 minutes results in no measurable removal of a carbon-doped low k dielectric layer. In other embodiments, the cleaning composition comprises about 10 to about 40 wt % TMAF and, optionally, about 0 to about 10 wt % HF, or about 0 to about 25 wt % TMAH. The cleaning composition can have a pH over a range of about 3.5 to about 14.
REFERENCES:
patent: 5698352 (1997-12-01), Ogawa et al.
patent: 5741626 (1998-04-01), Jain et al.
patent: 5783495 (1998-07-01), Li et al.
patent: 5981401 (1999-11-01), Torek et al.
patent: 6044851 (2000-04-01), Grieger et al.
patent: 6103637 (2000-08-01), Torek et al.
patent: 6107686 (2000-08-01), Sandhu et al.
patent: 6114259 (2000-09-01), Sukharev et al.
patent: 6144083 (2000-11-01), Yin
patent: 6156674 (2000-12-01), Li et al.
patent: 6162738 (2000-12-01), Chen et al.
patent: 6174590 (2001-01-01), Iyer et al.
patent: 6194315 (2001-02-01), Hu et al.
patent: 6225671 (2001-05-01), Yin
patent: 6268282 (2001-07-01), Sandhu et al.
patent: 6274292 (2001-08-01), Holscher et al.
patent: 6281100 (2001-08-01), Yin et al.
patent: 6291363 (2001-09-01), Yin et al.
patent: 6294457 (2001-09-01), Liu
patent: 6294459 (2001-09-01), Yin et al.
patent: 6319835 (2001-11-01), Sahbari et al.
patent: 6350700 (2002-02-01), Schinella et al.
patent: 6372614 (2002-04-01), Rangarajan et al.
patent: 6380096 (2002-04-01), Hung et al.
patent: 6391768 (2002-05-01), Lee et al.
patent: 6391794 (2002-05-01), Chen et al.
patent: 6410437 (2002-06-01), Flanner et al.
patent: 6417112 (2002-07-01), Peyne et al.
Chen Gary
Yin Zhiping
Hoang Quoc
Whyte Hirschboeck Dudek SC
LandOfFree
Dry low k film application for interlevel dielectric and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dry low k film application for interlevel dielectric and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dry low k film application for interlevel dielectric and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3128327