Dry etching method and a TFT fabrication method

Details Dry etching method and a TFT fabrication method Dry etching method and a TFT fabrication method

1999-03-18

2001-07-10

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S149000

Reexamination Certificate

active

06258723

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a dry etching method, and in particular to a dry etching method used in a thin-film transistor (TFT) fabrication process for a liquid crystal display.
BACKGROUND OF THE INVENTION
Generally, in semiconductor fabrication processing, to provide metal wiring on a silicon layer, including a hydrogenated amorphous silicon layer (a-Si:H) or on an isolation or insulation layer, a metal wiring layer on an underlayer must be selectively etched. If not otherwise specified, the “a-Si:H layer” in this specification is composed of a non-doped amorphous layer, a doped amorphous layer or both.
For example, in the procedures for fabricating a thin-film transistor (TFT) employed for a liquid crystal display (LCD), that has the structure shown in
FIG. 1
, a metal wiring layer
2
on an n type a-Si:H layer
1
, which is an underlayer, must be selectively etched. The TFT in
FIG. 1
is a so-called reverse staggered TFT, a gate electrode
6
wherefore is formed under an a-Si:H active layer (a channel layer)
4
on a substrate
7
.
Wet etching is normally employed to selectively etch the metal layer
2
. As one reason for this, in the dry etching process, when the metal layer is etched, etching of the underlayer also occurs, so that a so-called under-cut will be formed in the n type a-Si:H layer
1
, and etching of an i-stopper layer
3
and a gate isolation or insulation layer
5
formed under it will also occur. The i-stopper layer
3
is an isolation or insulation layer, for example, a silicon nitride layer formed between the source and the drain of the a-Si:H active layer
4
in order to prevent current leakage between the source and the drain while TFT is off. Another reason wet etching is employed in the prior art is that when using the dry etching process it is difficult to form the tapered end or edge that is required for the metal wiring, and specifically, the range is very narrow within which etching conditions can be established that satisfy both the requirement for selective etching and the requirement for a tapered wiring end or edge.
On the other hand, the dry etching method is employed to etch the n type a-Si:H layer
1
and the a-Si:H active layer
4
, which are underlayers for the metal layer
2
. One of the reasons for this is that a dry etching method for selectively etching the n type a-Si:H layer
1
on the i-stopper layer
3
and a dry etching method for selectively etching the a-Si:H active layer
4
on the gate isolation layer
5
are commonly established.
As is described above, in the fabrication processing for TFT shown in
FIG. 1
, conventionally, wet etching must be employed to etch the metal wiring layer
2
, and the dry etching must be employed to etch the n type a-Si:H layer
1
and the a-Si:H active layer
4
, which are the underlayers for the metal layer
2
. In other words, two different devices or tools, a wet etching tool and a dry etching tool, are required. Therefore, after the metal layer
2
has been etched, a substrate
7
must be removed from the wet etching device and then be set up in the dry etching device for the etching of the a-Si:H layers
1
and
4
. Since the substrate
7
comes into contact with the external atmosphere under normal atmospheric pressure, dust and impurities may attach themselves to its surface. In addition, the etching period is extended because the substrate must be loaded and unloaded twice and must be transported between the devicesor tools.
These problems can be resolved by etching the metal layer
2
first and then etching the a-Si:H layers
1
and
4
in the same dry etching device.
Described in Japanese Unexamined Patent Publication No. Hei
6-291314
is a TFT fabrication method whereby, in a plasma etching device, a gate isolation layer is etched under the same conditions as those under which a molybdenum metal layer (a gate electrode layer) is etched. The purpose of this method, however, is the etching of a gate isolation layer made of silicon nitride, and not the selective etching of a metal layer on an a-Si:H underlayer.
It is, therefore, one object of the present invention to provide a dry etching method whereby a metal layer and an a-Si:H underlayer are sequentially etched in a single etching device.
It is another object of the present invention to provide a dry etching method whereby a metal wiring layer on an a-Si:H underlayer can be selectively etched, and the end, sidewall or edge of the metal wiring layer can be tapered as required.
It is an additional object of the present invention to provide a dry etching method, used for a fabrication method for a TFT employed for a liquid crystal display, whereby a metal wiring layer on an a-Si:H underlayer can be selectively etched, and the end of the metal wiring can be tapered.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for etching in a dry etching device a hydrogenated amorphous silicon layer and a metal layer formed thereon is described comprising the steps of: selectively etching the metal layer on the hydrogenated amorphous silicon layer; and etching the hydrogenated amorphous silicon layer.
Furthermore, according to the present invention, a TFT fabrication method employing the above selective etching method is provided.


REFERENCES:
patent: 5017983 (1991-05-01), Wu
patent: 5516712 (1996-05-01), Wei et al.
patent: 5998229 (1999-12-01), Lyu et al.
patent: 6104042 (2000-08-01), Sah
patent: 1-274431 (1989-11-01), None
patent: 4-96223 (1992-03-01), None
patent: 6-177083 (1994-06-01), None

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