Dropout resistant phase-locked loop

Details Dropout resistant phase-locked loop Dropout resistant phase-locked loop

1999-04-02

2004-08-10

Deppe, Betsy L. (Department: 2734)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S340000

Reexamination Certificate

active

06775344

ABSTRACT:

TECHNICAL FIELD
The present invention relates to generating a data clock synchronized to a received data signal in the presence of data signal dropout.
BACKGROUND ART
Digital information may be represented by analog pulses in a data signal. Recovery of the digital information requires sampling the data signal at a particular instant during the time period for each analog pulse. A data clock is used to determine the sampling time. For correct sampling, the data clock needs to be synchronized with the received data signal.
A phased-locked loop (PLL) is often used to synchronize the data clock to the received data signal. These PLLs generally include a phase detector for determining the phase difference between pulses in the data signal and corresponding edges in the data clock. The phase difference produced by the phase detector is processed by a loop error controller. The loop error controller includes a filter/compensator for determining the dynamic response of the PLL. A voltage controlled oscillator (VCO) outputs the data clock based on the filtered phase difference signal. There are many designs for PLLs. In one design, a charge pump uses the phase difference signal to drive a single-ended analog filter/compensator circuit. In another design, the loop error controller includes a differential charge pump which uses the phase difference signal to drive an analog differential filter/compensator with a charge source and a charge sink. Correction circuitry uses a common mode output of the differential/compensator to drive a low voltage correcting charge pump and a high voltage correcting charge pump to keep voltage levels within preset limits.
The presence of dropout in the received data signal affects the ability to recover digital information. Dropout is the decrease in the signal amplitude of the received data signal. When the data signal results from reading magnetic tape, dropout may be caused by defects in the magnetic tape. These defects may weaken magnetic field transitions on the tape. Defects may also increase the distance between the magnetic tape and read and write heads. In addition to a decrease in the read signal amplitude envelope, a reduction in high frequency components due to dropout changes the shape of pulses in the read signal making correct detection of data more difficult. In particular, the phase detector may not be able to determine the phase difference between the data clock and weakened pulses in the data signal. This permits a phase error to accumulate which drives the PLL out of lock resulting in the loss of data bits until synchronization is again obtained. The loss of data bits expends error correction capability and may require a portion of the tape to be replayed.
Previous solutions to compensating for dropout in a PLL have concentrated on minimizing frequency drift in analog synchronous receivers. In these systems, the PLL is used to generate a local carrier frequency for synchronous demodulation. Minimizing frequency drift is not sufficient in digital detection because it permits phase shift resulting in duplicated or missed sampling.
What is needed is a dropout resistant data clock synchronized to the received data signal. The data clock should include a PLL that holds the data clock frequency constant and minimizes phase shift during periods of decreased data signal quality occurring during dropout. Such a system should be economical to produce and be easily integrated into existing magnetic tape read/write systems.
DISCLOSURE OF INVENTION
It is an object of the present invention to provide for generating a dropout resistant data clock synchronized to a received data signal.
Another object of the present invention is to provide a dropout resistant PLL that holds the data clock frequency constant and minimizes phase shift during periods of decreased data signal quality.
Still another object of the present invention is to provide for reading magnetic tape in the presence of dropout.
Yet another object of the present invention is to provide for economical dropout compensation.
In carrying out the above objects and other objects and features of the present invention, a dropout resistant system for generating a data clock synchronized to a received data signal is provided. The system includes a phase-locked loop for outputting the data clock with frequency and phase based on phase difference between the data signal and the data clock. The phase-locked loop holds constant the data clock frequency during periods when at least one indication of data signal quality falls outside of at least one threshold level.
In an embodiment of the present invention, the PLL resumes outputting data clock frequency and phase based on phase difference between the data signal and the data clock after a preset delay time from when the data signal quality indication returns within the at least one threshold level.
In another embodiment of the present invention, the data signal quality indication is based on at least one of the data signal amplitude envelope, the phase difference, the data signal distortion, the data signal frequency composition, a data stream resulting from detecting the data signal, and phase difference between the data clock and a normalized data clock, the normalized data clock based on relative phase amongst data clocks from a plurality of data signals.
A dropout resistant phase-locked loop is also provided. The PLL includes a phase detector for outputting a phase difference signal indicating phase difference between the data signal and the data clock when a disable signal is not asserted and indicating zero phase difference between the data signal and the data clock when the disable signal is asserted. A loop error controller inputs the phase difference signal and outputs a filtered phase difference signal. A voltage controlled oscillator inputs the filtered phase difference signal and outputs the read clock. A comparison system generates the disable signal based on at least one data signal quality indication and at least one threshold level. The comparison system asserts the disable signal when at least one data signal quality indication falls outside of at least one threshold level and deasserts the disable signal otherwise.
In an embodiment of the present invention, the loop error controller includes a charge pump for sourcing and sinking charge based on the phase difference signal. A filter/compensator outputs the filtered phase difference signal based on charge sourced and sinked by the charge pump.
In another embodiment of the present invention, the loop error controller includes a differential charge pump outputting a switched charge source and a switched charge sink based on the phase difference signal. A differential filter/compensator outputs the filtered phase difference signal based on the switched charged source and switched charged sink. The differential filter/compensator also outputs a common mode signal indicating voltage levels within the differential filter/ compensator. A high voltage correcting charge pump and a low voltage correcting charge pump lower and raise common mode voltage respectively in the differential filter/compensator based on voltage correction signals. A common mode correction circuit generates voltage correction signals based on the common mode signal when the disable signal is not asserted and disables correcting charge pumps when the disable signal is asserted.
A system for reading data recorded on magnetic tape is also provided. The system includes a read head for generating a read signal based on field transitions written on the magnetic tape as the magnetic tape moves by the read head. Conditioning electronics amplify and equalize the read signal. A comparison system asserts a disable signal when read signal quality falls outside of at least one threshold level and deasserts the disable signal otherwise. A data detector generates a data stream from the condition read signal based on a data clock. A phase-locked loop outputs the data clock having frequency and phase based on phase difference between the

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