Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
1999-03-04
2001-09-25
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C438S011000
Reexamination Certificate
active
06294397
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a drop-in test structure fabricated upon an integrated circuit topography for characterizing an integrated circuit production methodology, an integrated circuit topography, and equipment used in forming the integrated circuit.
2. Description of the Related Art
Fabrication of integrated circuits requires that precisely controlled quantities of impurities be introduced into small regions of a semiconductive substrate and that these regions be interconnected to create microelectronic components and integrated circuits. The patterns used to define such regions and interconnections are created using lithographic processes. To form the patterns, layers of photoresist material are applied as thin films to the upper surfaces of the substrate or to elevational profiles successively built upon the substrate. The photoresist is selectively exposed to a form of radiation such as specific optical wavelengths, ultraviolet light (“UV light”), X rays, or electrons. An exposure tool and mask are used to effect the exposure to UV light or X rays, while a data tape is used in electron beam lithography.
The exposure mask includes clear and opaque regions that define the features to be patterned in the photoresist. Areas of the photoresist exposed to radiation may be rendered preferentially soluble or insoluble, relative to unexposed photoresist, in a developing solvent. The change in solubility depends upon the type of photoresist used. Following development of the photoresist, the patterned photoresist is used as a mask during removal of exposed portions of the underlying substrate or conductive materials such as polycrystalline silicon or metal. As such, the pattern is transferred from the exposure mask to the integrated circuit topography.
Projection printing is the predominant method used for optically transferring a pattern from an exposure mask to a photoresist-coated wafer. In projection printing, wafers are separated from the masks by large distances. Lens elements or mirrors are used to focus the mask image onto the photoresist. Current projection printing systems use refractive optics to project the mask image onto the photoresist. Because it is impractical to build a refractive lens capable of projecting an image across an entire wafer, refractive systems project the image across a portion of the wafer. The projection field is then moved across the wafer using a “step-and-repeat” procedure. Masks used with step-and-repeat aligners are commonly referred to as “reticles” to distinguish them from masks that project images across an entire wafer.
The manufacture of semiconductor integrated circuits involves a loss of chip yield due to the presence of various defects. The two basic types of defects that may occur when conductive layers are formed on an integrated circuit are extra material defects (“EMD”) and missing material defects (“MMD”). EMD may occur when the conductive structures include material extending beyond predefined boundaries. Such material may extend to another conductive structure, causing a “short” to be formed between the two conductive structures. MMD may occur when a gap is formed in a conductive structure. Such a defect may cause the formation of an “open” conductive structure in which the continuity of the conductive structure is broken.
Defects that occur in a regular or repeating pattern typically result from shortcomings in the processing methodology, such as misalignment of a reticle or tilt of the wafer. These defects are known as systematic defects. In contrast, random defects occur without a pattern. Both EMD and MMD may be either systematic or random defects. For example, systematic problems in step coverage across areas of large elevational disparity may lead to the formation of open circuits due to missing material at the step. As another example, short circuits may be formed due to random distribution of particulate matter upon the die (which may result in connections between adjacent conductive lines) or upon the reticle used to pattern the die (which may result in conductive material between adjacent lines being retained rather than removed due to undesired masking by the particulate matter).
In order to detect defects that arise during fabrication of integrated circuits, test structures may be formed upon designated sites on a semiconductor wafer. Formation of the test structures may include multiple processing steps different from processes used to form production integrated circuits. For example, different reticles may be used to pattern successive layers of the test structures than are used to pattern the production die. As such, the elevational profile of a test structure that includes multiple layers of patterned conductive material may differ from the elevational profile of neighboring integrated circuits. Consequently, such test structures may not give an accurate indication of systematic problems that may occur due to elevational disparity in the production integrated circuit or random problems that occur in a production setting.
Alternatively, a small area within a production die may be reserved for a test device or devices. Test devices so formed may avoid the problems associated with using non-production reticles for successive layers of the test elevational profile. Forming test structures as part of a production die, however, significantly reduces the area available for the test structures. As such, random defects occurring with low frequency might not be detected.
SUMMARY OF THE INVENTION
The problems outlined above may be solved by the technique hereof for forming and using a test structure with a virtual integrated circuit methodology (“virtual methodology”) and a virtual integrated circuit elevational profile (“virtual elevational profile” or “virtual profile”) formed using the virtual methodology. The virtual methodology and topography may be used for characterizing a production integrated circuit methodology (“production methodology”) and a production integrated circuit topography (“production topography”) formed using the production methodology. The virtual methodology and topography may also be used to evaluate equipment for forming the production topography. As used in this application, “production integrated circuit topography” describes a topography that is contained within a packaged integrated circuit intended for use by a consumer of a product including the integrated circuit as an integral component. That is, a production topography is descriptive of an integrated circuit die that has been scribed, separated from a wafer, tested, packaged, and shipped. “Production integrated circuit fabrication methodology” describes a process for fabricating a production integrated circuit topography.
“Virtual integrated circuit elevational profile” as used in this application refers to a set of sequentially formed elevational features encompassing a subset of a production topography. That is, a virtual profile is formed according to a subset of the sequence of steps constituting the production methodology, whereas a production topography is formed according to a complete production methodology sequence. A virtual elevational profile is elevationally similar to a production topography, i.e., a virtual topography possesses a subset of the elevational features of a production topography such as transistor gate structures and interconnects. A virtual topography may lack, however, features such as source and drain dopants that do not influence the elevational profile of the topography. “Virtual integrated circuit methodology” describes a process for fabricating a virtual integrated circuit topography. A virtual methodology omits from a corresponding production methodology steps that do not affect elevational characteristics of the resulting topography and/or do not negatively impact the electrical or mechanical characteristics of the resulting topography. As such, a virtual topography emulates a production to
Emami Iraj
Jarvis Richard W.
May Charles E.
Advanced Micro Devices , Inc.
Bowers Charles
Conley & Rose & Tayon P.C.
Daffer Kevin L.
Kielin Erik
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