Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-11-04
2001-10-30
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000, C345S100000, C345S214000
Reexamination Certificate
active
06310594
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to pixel display circuits and, more particularly, to a method for driving these circuits to provide integrated data and gate multiplexing.
2. Description of the Related Art
Due to poor charging ability in amorphous silicon thin film transistors (a-Si TFTs) resulting from inherently low TFT transconductance, all commercially available a-Si TFT liquid crystal displays (LCD) include an array of pixel elements connected with row and column metal lines. The row and column drivers require higher transconductance devices. The row and column drivers typically include crystalline silicon technology and are separately fabricated and attached to the a-Si TFT LCDs. Over the years, there have been attempts at integrating some level of multiplexing between the attached crystalline silicon drivers and the pixel array. See for example, U.S. Pat. No. 5,175,446 to R. Stewart. In this way, the number of crystalline drivers needed could be reduced. These prior art designs follow a circuit approach that is commonly used in crystalline silicon circuit designs. Even simple 2:1 level multiplexing schemes at the edge of a pixel array have not been implemented for a-Si TFT LCD circuits. Although not realized for direct view a-Si TFT LCDs, multiplexer circuits have been implemented with some success in smaller displays for example, in light valves and in poly-silicon technology. Poly-silicon TFTs make it possible to realize a higher transconductance TFT. However, implementing poly-silicon technology on larger and/or high resolution TFT LCDs becomes unacceptable due to higher RC load and/or higher bandwidth rates of the rows and columns.
Therefore, a need exists for a control circuit for providing integrated data and gate multiplexing for active matrix LCDs without impacting acceptable display limits. A further need exists for a method of driving these displays which compensates for feedthrough voltage, an effective value and gate waveform delay.
SUMMARY OF THE INVENTION
A driving method for multiplexing pixels in active matrix displays in accordance with the present invention includes the steps of providing a plurality of pixels arranged in an array, wherein each pixel includes at least two transistors associated therewith, the transistors disposed in the array of pixels and each pixel including a plurality of control lines for controlling the transistors for turning each pixel on and off and sequencing waveforms on the control lines to provide multiplexing at the pixels in the array.
In alternate methods, the control lines include enable and row lines and a step of sequencing waveforms may further include the step of adjusting timing sequences of the waveforms wherein at least one pair of an adjacent enable line and row line are activated simultaneously to create a conducting path, through the at least two transistors, between a data line and a storage node. The step of activating the control lines by employing a gate driver may be included. The gate driver may include a plurality of outputs and the step of connecting the outputs of the gate driver in parallel with a plurality of control lines may also be included. The control lines may include row lines connected to gates of one of the at least two transistors and enable lines connected to gates of another transistor of the at least two transistors, the row lines and enable lines being alternately disposed within the array of pixels and the method may further include the step of providing waveforms on the enable lines having a fall time after a fall time of an adjacent row line wherein a difference in fall times ensures proper discharge and turn off of the gates of the transistors.
The driving method may include row lines and may further include the steps of providing storage capacitors having a charging electrode and a counter electrode, the charging electrode coupled to one of the at least two transistors for each pixel and the counter electrode including a first row line and compensating for feedthrough voltage on the storage capacitor by providing a negative (positive) pulse on the first row line while charging the charging electrode with a positive (negative) pulse on a second row line. The driving method may include row lines and further include the steps of providing storage capacitors having a charging electrode and a counter electrode, the charging electrode coupled to one of the at least two transistors for each pixel and the counter electrode including a first row line and compensating for an effective value of a data line voltage by providing a negative (positive) pulse on the first row line while charging the charging electrode with a positive (negative) pulse on a second row line. The step of adjusting signal delay on controls lines between pixels may also be included. The step of sequencing waveforms may include the step of addressing half of the pixels in a first time subframe and a second half of the pixels in a second time subframe. The array preferably includes columns of pixels and the method may further include the step of addressing the pixels in a first set of alternating column pairs of pixels in a first set of time slots and addressing a second set of alternating column pairs of pixels in a second set of time slots such that all pixels in the array are addressed in the first and second sets of time slots. The array preferably includes rows of pixels and the method may further include the step of addressing the pixels in the alternating column pairs for each pair of rows of pixels. The array preferably includes columns of pixels and the method may further include the step of addressing the pixels in a first set of alternating column pairs of pixels in a first time subframe and addressing a second set of alternating column pairs of pixels in a next consecutive time subframe such that all pixels in the array are addressed in the first and next consecutive time subframes. The pixels may be grouped in dot pairs and the method may further include the step of addressing the pixels in a first half of dot pairs of pixels in a first time subframe and addressing a second half of dot pairs of pixels in a next consecutive time subframe such that all pixels in the array are addressed in the first and next consecutive time subframes.
A circuit for addressing pixels in a pixel array in accordance with the present invention includes at least two transistors associated with each pixel, the transistors disposed in the array of pixels. A plurality of control lines associated with each pixel for controlling the transistors of each pixel. At least one gate driver sequences waveforms on the control lines to provide multiplexing at the pixels in the array.
In alternate embodiments of the circuit, the control lines may include enable and row lines such that at least one pair of an adjacent enable line and row line are activated simultaneously to create a conducting path through the at least two transistors between a data line and a storage capacitor. The gate driver may include a semiconductor chip. The gate driver preferably includes a plurality of outputs, and the outputs of the gate driver may be connected in parallel with a plurality of control lines. The control lines may include row lines connected to gates of one of the at least two transistors and enable lines connected to gates of another transistor of the at least two transistors, the row lines and enable lines being alternately disposed within the array of pixels and shared between adjacent rows of pixels. The at least two transistors preferably include thin film transistors. The circuit may include two gate drivers. The at least one gate driver may have outputs split into a first group and a second group such that a duty cycle and a capacitive load for the outputs is reduced by one half. The circuit for addressing pixels may include an integrated circuit.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative em
Libsch Frank R.
Schleupen Kai R.
Wisnieff Robert L.
F. Chau & Associates LLP
International Business Machines - Corporation
Said Mansour M.
Shalwala Bipin
LandOfFree
Driving method and circuit for pixel multiplexing circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Driving method and circuit for pixel multiplexing circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Driving method and circuit for pixel multiplexing circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2617642