Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-09-21
2003-04-15
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185230
Reexamination Certificate
active
06549461
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
This application relies for priority upon Korean Patent Application Nos. 2000-55795, filed on Sep. 22, 2000 and 2001-08692, filed on Feb. 21, 2001, the contents of which are hereby incorporated herein by reference in their entirety as if fully set forth herein.
BACKGROUND
1. Field of the Invention
The present invention generally relates to nonvolatile semiconductor memory devices, and more particularly to driving circuits of non-volatile semiconductor memory devices.
2. Description of the Related Art
NAND-type flash memories have advantages as much as dynamic RAMs as a kind of a nonvolatile semiconductor memory device arising from high integration levels and great capacity. The NAND flash memory basically includes a memory cell array constructed of plural memory strings each of which is formed of plural memory cells connected between a bitline and a source line in series. The memory cells coupled to a wordline form a unit of a page or a byte.
In programming memory cells, a high-level programming voltage of about 15~20V is applied to a selected wordline while a power supply voltage (or a voltage greater than the power supply voltage) is applied to a bitline connected to a non-selected memory cell so as to prevent the non-selected memory cell from being programmed in the same page. Such a programming inhibition technique increases the channel voltage of the non-selected memory cell which is not to be programmed, and thereby suppresses a tunneling effect of electrons therein by the high-level programming voltage applied through the wordline. However, a problem occurs due to an insufficient channel voltage than that required for programming inhibition, because the programming inhibition voltage is lowered through a selection transistor in accordance with a lower power supply voltage.
For the purpose of overcoming the problem due to a low power supply condition, there has been developed a way to charge a source line up to a power supply voltage, or a greater voltage level so as to enhance an effect of the programming inhibition (refer to pp. 234~235 of “1998
Symposium on VLSI Circuits Digest of Technical Papers”
). The source line (or common source line) is set to a ground voltage during a read operation, and maintains a floating state (no voltage bias) during an erasure operation to reduce a stress due to a erasure voltage. The reason that the power supply voltage, or a greater voltage level is applied to the source line is to offset a voltage reduction from the low power supply voltage.
However, as shown in
FIG. 1
, the source line is connected to all of the memory strings over the whole memory cell array (e.g., see Japanese Patent Publication No. 11-31392, or U.S. Pat. No. 6,058,044). A common source line CSL is arranged over an entire memory cell array to transfer a source line voltage VCSL supplied from a driver CD to memory cell array units MCUs at a time. Each of the wordline drivers WDs, each being assigned to a corresponding memory cell array unit MCU, receives a signal EN to activate a high voltage generator (or a charge pump) therein which generates a programming voltage, a wordline drive signal Si, a high voltage source HV, a voltage VSSL applied to a string selection line, and a voltage VGSL applied to a ground selection line. Therefore, outputs from the wordline driver WD are connected to 32 wordlines divided into two memory strings, two string selection lines for selecting two memory strings, and one ground selection line which is shared by two memory strings.
In a programming operation, a portion (e.g., one) of the memory strings is selected in the memory cell array unit MCU by alternative activation of the signal EN having address decoding information and the string selection signal SSL, and a memory cell in a selected memory string is selected to be programmed. However, during the programming mode, the source line voltage VCSL is applied to sources of ground selection transistors in all of the memory strings, regardless of whether the strings are selected or non-selected for programming. That is, although only a portion of the memory strings are selected for programming, the entire common source line arranged over the entire memory cell array is driven with the source line voltage VCSL. Therefore, it is necessary to overcome a great load due to resistance and capacitance, i.e., an RC parameter, existing along the source line.
In particular, in contrast to the method wherein the power supply voltage is supplied only to the bitline for the programming inhibition, the need to apply the power supply voltage, or a greater voltage level, to the common source line as well as the bitline causes an increase in the programming time due to RC loads or propagation delays. While a high capacity driver (e.g., a CSL driver having a charge pump) or a voltage amplifier may be employed to counteract the voltage and time loss due to the RC effects, this would increase the circuit area and thereby be unsuitable for a higher capacity and/or a lower power NAND flash memory.
In the meantime, a high voltage greater than the power supply voltage is applied to a control gate of a selected memory cell through a selected wordline from the wordline driver to conduct operations of programming, erasing, or reading data of memory cells. Referring to
FIG. 2
, driving circuits
9
and
10
, the same as those shown in
FIG. 1
, are arranged in correspondence with memory cell array units MCUs. Transmission transistors SN
0
, WN
0
~WN
15
, and GN
0
(or SN
1
, WN
16
~WN
31
and GN
1
) are interposed between a memory cell array and signal lines of the string and ground selection signals, and wordline drive signals, all supplied from a wordline predecoder
5
. And, a high voltage VGPt (or VGPb) generated from a high voltage controller HVCt (or HVCb) is applied to gates of the transmission transistors SN
0
, WN
0
~WN
15
, and GN
0
(or SN
1
, WN
16
~WN
31
, and GN
1
), in order to transfer the signals to the memory cell array unit without voltage loss. The high voltage controller receives a high voltage HV supplied from a generator
3
, together with the predecoder
5
.
As the number of wordlines to be selected at a time increases in accordance with a higher integration density of a memory device, the driving circuits occupy more and more area on the device. Substantially, the effort to produce a high integration is usually concentrated on the region of the memory cell arrays, while a memory cell occupies a smaller circuit region. On the other hand, the peripheral circuits, such as the driving circuits, are not so much positioned in a smaller circuit region as the memory cell array is, according to a higher integration of the memory cell array. Thus, the arrangement that each memory cell array unit is assigned to each high voltage controller (or switching circuit) is not helpful to enhance an integration density of the NAND flash memory device.
SUMMARY
It is, therefore, an object of the present invention to provide a NAND flash memory device capable of efficiently performing a programming inhibition function.
It is another object of the present invention to provide a NAND flash memory device capable of performing a reliable programming inhibition function, even in the condition of a lower power supply voltage.
It is another object of the present invention to provide a NAND flash memory device capable of reducing loads on a source line which is connected to a memory cell array.
It is another object of the present invention to provide a NAND flash memory device capable of efficiently decoding memory cells with a smaller circuit region.
In order to attain the above objects, according to an aspect of the present invention, there is provided a NAND flash memory device including: a plurality of memory cell array units, each memory cell array unit having a plurality of memory strings, each memory string having a string selection line, a ground selection line, and a plurality of wordlines; a plurality of source lines divisionally arranged in the memory cell array uni
Kwon Suk Cheon
Lim Young Ho
Park Jung Hoon
Samsung Electronics Co,. Ltd.
Tran M.
Volentine & Francos, PLLC
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