Driving circuit for non destructive non volatile...

Details Driving circuit for non destructive non volatile... Driving circuit for non destructive non volatile...

2001-07-09

2002-05-21

Phan, Trong (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000

Reexamination Certificate

active

06392921

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driving circuit for a non destructive non volatile ferroelectric random access memory (hereinafter, it is referred to a NDRO-FRAM), in particular to a driving circuit for a NDRO-FRAM which is capable of reading and writing on the NDRO-FRAM by comprising a word line decoder and a writing driver.
2. Description of the Prior Art
FIG. 1
illustrates a driving circuit for a memory in accordance with the conventional technology. It comprises a pre-charge circuit
1
, a equalization circuit
2
, memory cells
3
a
~
3
n
, word lines
4
a
~
4
n
, a transmission gate
5
, a sense amp
6
, a data output circuit
7
, bit lines
8
a
,
8
b
, and data bus lines
9
a
,
9
b.
DRAMs separately constructed with a metal-silicon oxide film-silicon field effect transistor and a metal-oxide film-a metal structure capacitor are used as the memory cells
3
a
~
3
n
, a column address decoding signal and a row address decoding signal (not shown in
FIG. 1
) are used in a structure arranged with the columns in order to write or read data on the one memory cell among the memory cells
3
a
~
3
n
. For example, in the memory cell reading operation, a certain memory cell is selected by selecting the word line inputted the column address decoding signal and the bit lines
8
a
,
8
b
inputted the row address decoding signal, the equalization circuit
2
equalizes the bit lines
8
a
,
8
b
, the transmission gate
5
receives data level of the certain memory cell displayed on the bit lines
8
a
,
8
b
and transmits it to the sense amp
6
. The sense amp
6
detects the received data level, amplifies it, and transmits it to the data output circuit
7
through the data bus lines
9
a
,
9
b
. The data output circuit
7
transmits the received data level to an external unit.
In the memory cell writing operation, a data input circuit (not shown in
FIG. 1
) is comprised on the behalf of the data output circuit
7
.
In general, the driving circuit of the memory performs the writing operation or reading operation by turning the transistor inside of the memory cell on by the one column address decoding and one row address decoding signal.
FIG. 2
illustrates signs illustrating a NDRO-FRAM cell of a 1 transistor type to be driven according to the embodiment of the present invention, it comprises a drain D, a gate G, a bulk B, and a source S. The driving condition of the NDRO-FRAM cell
2
will now be described in Table 1.
[TABLE 1]
DRAIN (D)
BULK (B)
SOURCE (S)
GATE (G)
READING
+Vcc
FLOATING
GROUNDING
FLOATING
OPERATION
WRITING
GROUNDING
GROUNDING
FLOATING
WHEN 1 IS WRITTEN
OPERATION
(+Vcc)
WHEN 0 IS WRITTEN
(−Vcc)
In the writing operation condition of the NDRO-FRAM cell
2
, both the drain and bulk are grounded, when 0 is written, −Vcc has to be applied to the gate, when 1 is written, +Vcc has to be applied to the gate in order to polarize polarized dipole existed on the ferroelectrics gate of the NDRO-FRAM cell
2
in accordance with polarity of +voltage or −voltage.
After writing data of 0 or 1 on the gate one time, there is no need to apply the gate voltage again, the NDRO-FRAM cell
2
continually stores the data of 0 or 1. In the reading operation condition of the NDRO-FRAM cell
2
, +Vcc is applied to the drain, the source is grounded, the bulk and gate are floated.
When 1 is written on the NDRO-FRAM cell
2
, the polarized dipole of the ferroelectrics gate formed already generates the effect same with a case applying the +voltage to the gate channel, according to this, the gate channel is ON and electric current is applied to the drain, accordingly the 1 data level can be read by detecting the electric current.
When 0 is written on the NDRO-FRAM cell
2
, the direction of the polarized dipole is reversed, it is as same as applying −voltage to the gate channel, the gate channel is OFF and the drain electric current can not flow, accordingly 0 data level is written.
As described above, differentiating from the conventional DRAM, the NDRO-FRAM cell having 1 transistor type has to apply the signal to the drain, gate, source, bulk in the reading and writing operation, accordingly the conventional driving circuit of
FIG. 1
can not perform the above-described operation.
SUMMARY OF THE INVENTION
In order to solve the above-mentioned problems, the object of the present invention is to provide a driving circuit which is capable of performing reading operation and writing operation on a non destructive non volatile ferroelectric random memory.


REFERENCES:
patent: 5812442 (1998-09-01), Yoo
patent: 6046927 (2000-04-01), Lee et al.
patent: 6242771 (2001-06-01), Hsu et al.

Affiliated with

Also associated with

Rating

Driving circuit for non destructive non volatile... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Driving circuit for non destructive non volatile..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Driving circuit for non destructive non volatile... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2893814