Driving circuit for LCD

Electronic digital logic circuitry – Interface – Current driving

Reexamination Certificate

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Details

C326S113000, C326S081000, C345S095000, C345S051000, C345S052000, C345S210000, C345S211000

Reexamination Certificate

active

06559677

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application claims the priority of Application No. 2000-354113, filed Nov. 21, 2000 in Japan, the subject matter of which is incorporated herein by reference.
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a driving circuit for driving an LCD (liquid crystal display) or the like.
BACKGROUND OF THE INVENTION
A conventional driving circuit is designed to drive segment electrodes in, for example, a matrix type LCD. According to a conventional driving circuit, a leakage current may flow between driving voltages via an output node. Although the leakage current caused in each driving circuit is small, as the number of driving circuits is increased in association with a trend toward a larger screen of the LCD, the total power consumption is increased. The increase in power consumption associated with the trend toward the larger screen is a serious problem especially in battery-powered portable displays.
OBJECTS OF THE INVENTION
Accordingly, it is an object of the present invention to provide a driving circuit in which the problems of the prior art are solved and in which no leakage current occurs in switching of a driving voltage.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
SUMMARY OF THE INVENTION
To solve the above problems, according to a first aspect of the present invention, there is provided a driving circuit having a plurality of switching units for, when receiving respective corresponding driving signals, outputting driving voltages corresponding to the driving signals to a common output node, the driving circuit including a driving control unit for, when a selection signal to select the driving voltage is activated, outputting the driving signal so as to be delayed by a predetermined time period and, when the selection signal is inactivated, immediately interrupting the driving signal.
Since the driving circuit is constructed as mentioned above, the following operation is performed.
For instance, when a selection signal to select a first driving voltage is inactivated at a certain instant and a selection signal to select a second driving voltage is activated, the driving control unit immediately interrupts a driving signal corresponding to the first driving voltage, thereby interrupting the first driving voltage generated from the switching unit. On the other hand, a driving signal corresponding to the second driving voltage is generated from the driving unit so as to be delayed by a predetermined time period. Consequently, after the first driving voltage is interrupted, the second driving voltage is generated from the switching unit after the predetermined time period.
According to a second aspect of the present invention, there is provided a driving circuit similar to that of the first aspect, the driving circuit including: selecting units for selecting a first clock signal when a selection signal to select a driving voltage is inactivated and, when the selection signal is activated, selecting a second clock signal delayed in phase relative to the first clock signal; and holding units for holding the selection signal on the basis of timing of the clock signal selected by the selecting unit and supplying the held contents as a driving signal to the switching unit.
In this aspect, the following operation is performed.
For example, when a selection signal to select a first driving voltage is inactivated at a certain instant and a selection signal to select a second driving voltage is activated, the selection signal corresponding to the first driving voltage is held by the holding unit at timing of the next first clock signal and, further, the selection signal corresponding to the second driving voltage is held by the holding unit at timing of the subsequent second clock signal. Consequently, the first driving voltage is interrupted at the timing of the first clock signal and, after that, the second driving voltage is outputted at the timing of the second clock signal.
According to a third aspect of the present invention, there is provided a driving circuit similar to that of the first aspect, the driving circuit including: selecting units similar to those of the second aspect of the present invention; holding units for holding a selection signal on the basis of timing of a clock signal selected by the selecting unit; and driving control units for, when the selection signal held by the holding circuit is activated, outputting the driving signal so as to be delayed by a predetermined time period and, when the selection signal is inactivated, immediately interrupting the driving signal.
In this aspect, the following operation is performed.
For instance, when a selection signal to select a first driving voltage is inactivated at a certain instant and a selection signal to select a second driving voltage is activated, the selection signal corresponding to the first driving voltage is held by the holding unit at timing of the next first clock signal and, further, the selection signal corresponding to the second driving voltage is held by the holding unit at timing of the subsequent second clock signal. As for the selection signals held by the holding units, the driving control units control delay time and each selection signal is supplied as a driving signal to the switching unit. Consequently, the first driving voltage is interrupted at the timing of the first clock signal and, after that, the second driving voltage is outputted so as to be further delayed relative to the timing of the second clock signal.
According to a fourth aspect of the present invention, there is provided a driving circuit similar to that of the first aspect, the driving circuit including: selecting units for selecting a first clock signal when an input signal is inactivated and, when the input signal is activated, selecting a second clock signal delayed in phase relative to the first clock signal; holding units for holding the input signal on the basis of timing of the clock signal selected by the selecting unit; and a decoding unit for decoding the held contents of the holding unit to form the driving signal for selecting the driving voltage and supply the driving signal to the switching unit.
In this aspect, the following operation is performed.
For example, when an input signal is inactivated at a certain instant, the selecting unit selects the first clock signal and the holding unit holds the input signal at timing of the next first clock signal. The held input signal is decoded by the decoding unit. A driving signal as a decoding result is supplied to the switching unit, thereby interrupting the corresponding driving voltage.
On the other hand, when the input signal is activated, the selecting unit selects the second clock signal delayed in phase relative to the first clock signal and the holding unit holds the input signal at timing of the next second clock signal. The input signal held by the holding unit is decoded by the decoding unit and a driving signal as a decoding result is supplied to the switching unit, thereby outputting the corresponding driving voltage.
According to a fifth aspect of the present invention, there is provided a driving circuit similar to that of the first aspect, the driving circuit including: selecting units and holding units similar to those of the fourth aspect; a decoding unit for decoding the held contents of the holding units to form a selection signal to select the driving voltage; and a driving control unit for, when the selection signal is activated, outputting the driving signal so as to be delayed by a predetermined time period, and when the selection signal is inactivated, immediately interrupting the

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