Driving circuit

Details Driving circuit Driving circuit

2002-12-03

2004-06-15

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S063000, C326S086000, C327S333000

Reexamination Certificate

active

06750676

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to a driving circuit, for example, a current output type driving circuit used in a bubble jet printer for supplying a driving current to heat a printer head part.
BACKGROUND OF THE INVENTION
At a head part of a bubble jet printer, a current is supplied to a heater to generate heat, and bubbles of ink are created in the nozzle of the header part by the heat and sprayed onto a paper surface. Usually, a driver circuit is provided at the head part in order to supply the current to the heater. In the past, the driver circuit was configured using bipolar transistors.
FIG. 6
is an outlined diagram showing an example configuration of the driving circuit. As shown in the figure, the driver circuit is configured with input buffer
10
, level conversion circuit
20
, driver part
30
, and current output part
40
. In terms of normal operating speed, when the driving circuit shown in
FIG. 6
is configured using CMOS transistors inferior to bipolar transistors, operating speed, in particular, specification of the output current characteristic at current output part
40
, becomes important.
Ideally, it is desirable if the driving current supplied to the heater by the driving circuit can be controlled through the input of control signal S
in
without any distortion. That is, the waveform of the driving current supplied to the heater needs to match roughly the waveform of control signal S
in.
However, when the driving circuit is actually configured using CMOS transistors, the waveform of the driving current output may differ from the waveform of input signal S
in
due to frequency characteristics and delay characteristics of the circuit.
FIG. 7
shows waveform diagrams showing example waveforms of input signal S
in
and driving current I
H
output from the driving circuit. As shown in the figure, rising time t
R
, falling time t
F
, rise delay time t
PLH
, and fall delay time t
PHL
in the waveform of driving urrent I
H
are of important specifications.
Rising time t
R
refers to the time required for driving current I
H
to go from 10% to 90% of maximum current value I
Hmax
, and falling time t
F
refers to the time required for driving current I
H
to fall from 90% to 10% of maximum current value I
Hmax
. In addition, rise delay time t
PLH
refers to the time the rising edge of the driving current is delayed from the rising edge of input signal S
in
, and fall delay time t
PHL
refers to the time the falling edge of the driving current is delayed from the falling edge of input signal S
in
.
FIG. 8
shows drain-source voltage V
ds
and drain current I
ds
characteristics of current output MOS transistor Q
H
used for output part
40
. The resistance of a MOS transistor when it is conductive, or so-called on-resistance, is determined by its gate-source voltage V
g
, and the on-resistance of the MOS transistor depends only on its gate-source voltage V
g
, not drain-source voltage V
ds
, except in saturated regions. In addition, drain current I
ds
of the MOS transistor, that is, driving current I
H
supplied to load resistor R
1
, is determined based on source voltage V
H
, load resistance value r1, and on-resistance r
ON
of the MOS transistor and is given by the following equation.
Equation 1
I
H
=V
H
/(
r
1
+r
ON
)  (1)
The dotted line in
FIG. 8
indicates the load characteristic of the heater connected to the drain of the MOS transistor. Here, assume that source voltage V
H
is 25V, and the resistance value of the heater is approximately 250&OHgr;.
As shown in
FIG. 8
, driving current I
H
supplied to the heater changes from 0 mA to approximately 100 mA according to gate voltage V
g
of the transistor.
The characteristics of gate voltage V
g
of current output transistor Q
H
and output current I
H
thereof with respect to input signal S
in
can be obtained based on the output characteristic and load characteristic of the MOS transistor for current output.
FIG. 9
shows respective waveforms of input signal S
in
, gate voltage V
g
of current output transistor Q
H
, and driving current I
H
. In addition, in
FIG. 9
, the relationship between rise delay time t
PLH
and fall delay time t
PHL
is also shown. As shown in
FIG. 9
, when the voltage is half the maximum value, for example, when the maximum value is the source voltage for input buffer
10
, that is, V
dd
=5V, at the rising edge of input signal S
in
, rise delay time t
PLH
refers to the delay time from when it has reached half of said value, that is, 2.5V, until gate voltage V
g
of current output transistor Q
H
reaches 6V, for example. Furthermore, here, assume that the maximum value of gate voltage V
g
of transistor Q
H
is approximately equal to source voltage V
H
, for example, 25V.
In addition, fall delay time t
PHL
refers to the time from when the voltage has reached half of maximum value V
dd
, that is, 2.5V, at the falling edge of input signal S
in
until gate voltage V
g
of transistor Q
H
drops to 6V.
In addition, rise delay time t
PLH
is approximately equal to the delay time from when input signal S
in
has reached half the maximum value until driving current I
H
reaches half the maximum value. On the other hand, fall delay time t
PHL
is approximately equal to the delay time from when input signal S
in
has reached half the maximum value until driving current I
H
reaches half the maximum value.
As shown in the figure, the time required for gate voltage V
g
of current output transistor Q
H
to rise from 0V to 6V is less than the time required for gate voltage V
g
to fall from the maximum value of 25V to 6V. That is, fall delay time t
PHL
>rise delay time t
PLH
.
Accordingly, when rising time t
R
and falling time t
F
of driving current I
H
to be output are made equal, fall delay time t
PHL
of driving current I
H
becomes longer than rise delay time t
PLH
with respect to input signal S
in
. That is, the balance between the rise and the fall of driving current I
H
deteriorates, and pulse width T
W-IH
of driving current I
H
becomes greater than pulse width T
W-IN
of input signal S
in
, so that driving current I
H
can no longer be controlled highly accurately.
The conventional driving circuit adopted a method that sets a short falling time in order to improve driving current controllability.
For example, as shown in
FIG. 10
, the times required for gate voltage V
g
of current output transistor Q
H
to start changing after input signal S
in
becomes half the maximum value at the rising edge and the falling edge of input signal S
in
are denoted as T
11
and T
21
, respectively, and set as T
11
=T
21
=10 ns. Furthermore, rising time T
R
and falling time T
F
of driving current I
H
of transistor Q
H
are set as T
R
=T
F
=20 ns.
As shown in
FIG. 10
, time T
12
required for gate voltage V
g
to rise to 6V is roughly ¼ of rising time T
R
, and time T
22
required for gate voltage V
g
to fall from the maximum value of 25V to 6V is roughly ¾ of falling time T
F
. That is, T
12
=5 ns, and T
22
=15 ns. Thus, rise delay time T
PLH
and fall delay time T
PHL
are obtained as follows, respectively. That is, T
PLH
=T
11
+T
12
=15 ns, and T
PHL
=T
21
+T
22
=25 ns. Accordingly, the difference between rise delay time T
PLH
and fall delay time T
PHL
is T
PLH
−T
PHL
=10 ns. For example, when pulse width T
w-in
of input signal S
in
is 100 ns, pulse width T
W-IH
of driving current I
H
becomes roughly 110 ns, creating a difference between the input and the output pulse widths, so that the timing of the driving current can not be controlled accurately.
Conventionally, a method for reducing falling time T
F
of driving current I
H
has been used in order to reduce fall delay time T
PHL
. However, said method is disadvantageous in that not only the symmetry between rising time T
R
and falling time T
F
is destroyed, but ringing also increases as undershoot increases at the falling edge of driving current I
H
when falling

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