Electric lamp and discharge devices: systems – Plural power supplies – Plural cathode and/or anode load device
Reexamination Certificate
2001-03-13
2002-08-27
Philogene, Haissa (Department: 2821)
Electric lamp and discharge devices: systems
Plural power supplies
Plural cathode and/or anode load device
C315S169200, C315S169100, C345S698000, C345S214000, C345S212000
Reexamination Certificate
active
06441562
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driving apparatus of a flat panel display, and more specifically, to a driving apparatus of a flat panel display having sub gate driver IC and sub source driver IC that compensate for distortion of the source and gate signals caused by transmission delay of the source and gate signals in flat panel display of a large size.
2. Description of the Related Art
Recently, flat panel displays such as liquid crystal display(LCD), plasma panel display, electroluminescence display panel take advantages of the smaller dimension, lighter weight and lower power consumption, and replace a traditional cathode ray tube(CRT).
Generally, driving signals for driving flat panel displays are supplied in a form of voltage or current that is proportional or inversely proportional to the brightness of the pixel unlike the operation method of CRT. The driving signals act as changing the panel electrically or optically. The driving signals are supplied from driving apparatus arranged adjacent to the panel.
Flat panel displays need the driving signals to be supplied without a signal distortion over the entire display area. To this end, various kinds of items should be considered in designing and processing the panel.
By continuous research and development in design and process technologies, many needs have been met step by step. However, in a flat panel display having a large screen, it is difficult to obtain a high definition and high quality in picture because of signal distortions caused by the time delay of transmission signals.
To overcome the drawback, a method for lowering the resistance of wires formed on the panel, for minimizing load by stray capacitance and decreasing load of adjacent circuits is provided.
The method, however, does not satisfy a desired requirement for wire resistance because of the limitations in the currently used material and process technology. Also, development of new material capable of satisfying the desired condition needs more time and may require new process equipments for the newly developed material. Moreover, the structural limitation of pixel makes it also difficult to decrease the stray capacitance below a critical value.
Thus, it is required to prevent picture quality degradation as the screen size of the flat panel display increases.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to obtain high quality of image over the entire screen area of a flat panel display of a large size screen.
It is another object of the present invention to compensate for distortion of driving signals during the signal transmission.
To achieve the above and other objects and advantages, there is provided a driving apparatus of a flat panel display comprising: a signal processing means for outputting a plurality of signals including display data, gray scale voltages, a gate On/Off voltage, a source control signal and a gate control signal with a driving data, a driving control signal, and a driving power source; a main source driver IC for generating and outputting a source signal using the display data, the gray scale voltages and the source control signal; a main gate driver IC for generating and outputting a gate signal using the gate On/Off signal and the gate control signal; a display panel having a plurality of pixels configured in a matrix arrangement, for displaying an image by selectively driving the pixels; a source feedback means arranged along a row direction of the display panel that is opposite said main source driver IC, for detecting distorted amount of a source signal output from a pixel placed at the last column of a source line connected to the main source driver IC and feeding back a first compensation signal corresponding to the distorted amount of the source signal to the pixel at the last column; and a gate feedback means arranged along a column direction of the display panel that is opposite said main gate driver IC, for detecting distorted amount of a gate signal output from a pixel placed at the last row of a gate line connected to the main gate driver IC and feeding back a second compensation signal corresponding to the distorted amount of the gate signal to the pixel at the last row.
It is desirous that the source feedback means comprises a plurality of sub-source driver ICs, each of said sub-source driver ICs having a plurality of first basic unit elements, each of said first basic unit blocks comprising: a first mixer for mixing source signal output from the last pixel placed at the last column of source signal transmission with the first compensation signal; a first differential circuit for differentiating an output of said first mixer; a first adder for adding the output of said first mixer and an output of said first differential circuit; and a first amplifier for amplifying an output of said first adder to a predetermined level and applying the amplified signal to the first mixer as said first compensation signal.
It is desirous that the first basic unit block further comprises: a first subtracter for comparing the output of said first adder with the output of said first mixer and outputting a difference signal corresponding to a difference between the output of said first adder and the output of said first mixer; and a first gain control part for controlling the outputs of said first differential circuit and said first adder with the output of said first subtracter, wherein the basic unit block restrains an oscillation generated from a first feedback loop consisting of said first differential circuit, said first adder and said first amplifier.
REFERENCES:
patent: 5434599 (1995-07-01), Hirai et al.
patent: 5598180 (1997-01-01), Suzuki et al.
patent: 5900856 (1999-05-01), Iino et al.
patent: 6072457 (2000-06-01), Hashimoto et al.
McGuireWoods LLP
Park Hae-Chan
Philogene Haissa
Samsung Electronics Co,. Ltd.
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