Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2002-08-29
2004-04-27
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S189090, C365S222000, C365S226000
Reexamination Certificate
active
06728151
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to circuits and methods for driving a dynamic random access memory (DRAM) sense amplifier. More particularly, this invention relates to circuits and methods for driving a DRAM sense amplifier having low threshold voltage p-channel metal-oxide semiconductor (PMOS) field-effect transistors.
Known DRAM circuits generally include the following: a plurality of dynamic memory cells each operative to store digital data (i.e., digital data bit “1” or digital data bit “0”); word lines operative to “select” and “deselect” the memory cells; and digital lines operative to read, write, and refresh the digital data of selected memory cells. Additionally, DRAM circuits include sense amplifier circuitry, sense amplifier driver circuitry, and various other peripheral circuitry (e.g., equalization and pre-charge circuitry, write circuitry, word line decoders, digital line decoders, etc.) that control DRAM operation.
Generally speaking, DRAM sense amplifier driver circuitry “activates” a sense amplifier during read, write, and refresh operations. An activated sense amplifier amplifies (i.e., increases) a differential voltage between a complimentary pair of digital lines to a full digital logic separation (i.e., a full digital “0” on the first digital line of the complimentary pair and a full digital “1” on the second digital line of the complimentary pair). Alternatively, DRAM sense amplifier driver circuitry “deactivates” the sense amplifier during DRAM standby mode (i.e., DRAM circuit operation pending a read, write, or refresh operation). A deactivated sense amplifier does not amplify and preferably does not affect the voltage potential between the complimentary pair of digital lines.
As feature size (e.g., transistor channel length) is reduced, an increased number of transistors can be included in an integrated circuit (IC) chip. For DRAM technology, an increased number of transistors can advantageously provide, for example, increased data storage capacity in a DRAM circuit (i.e., additional memory cells). However, because the number of transistors on an IC chip is directly proportional to power consumption by the IC chip, any significant increase in the number of transistors on an IC chip is preferably accompanied by a reduction in the voltage supplied to the IC chip, which reduces power consumption by the IC chip. Such a voltage reduction is generally accompanied by a decrease in the threshold voltage of each transistor (i.e., voltage at which a transistor becomes conductive or turns “ON”).
Known DRAM sense amplifier driver circuits are not well-suited for driving DRAM sense amplifiers having low threshold voltage PMOS transistors. Such known driver circuits cause significant sub-threshold current loss through sense amplifiers having low threshold voltage PMOS transistors. Sub-threshold current loss through a DRAM sense amplifier undesirably increases power consumption, increases the time required for a read, write, and refresh operation, and can cause erroneous reading and refreshing of digital data.
In view of the foregoing, it would be desirable to provide improved circuits and methods for driving a DRAM sense amplifier having low threshold voltage PMOS transistors.
SUMMARY OF THE INVENTION
It is an object of the invention to provide improved circuits and methods for driving a DRAM sense amplifier having low threshold voltage PMOS transistors.
Improved electrical circuits for driving a DRAM sense amplifier having low threshold voltage (V
tp
) PMOS transistors are provided in accordance with the invention. Electrical circuitry is provided that maintains the source terminal of a PMOS transistor of a DRAM sense amplifier at ground potential during DRAM standby mode. In one embodiment, the electrical circuitry pulls-down the source terminal of the PMOS transistor to ground potential in response to an EQ line transition to digital “1.” In another embodiment, the electrical circuitry pulls-down the source terminal of the PMOS transistor to ground potential in response to both an EQ line transition to digital “1” and a /WLEN line transition to digital “1.” In still another embodiment, the electrical circuitry pulls-down the source terminal of the PMOS transistor to ground potential in response to both a /PSA line transition to digital “1” and a /WLEN line transition to digital “1.” Maintaining the source terminal of the PMOS transistor at ground potential during DRAM standby mode limits current bleed through the PMOS transistor in the event of a word line and digital line short-circuit.
Electrical circuitry is also provided that raises the source terminal of the PMOS transistor to an intermediate supply voltage in response to a transition from DRAM standby mode to either DRAM read mode, DRAM write mode, or DRAM refresh mode and prior to development of a differential voltage between the gate and drain terminals of the PMOS transistor. In one embodiment, the electrical circuitry raises the source terminal of the PMOS transistor to the intermediate voltage in response to an EQ line transition to digital “0.” In another embodiment, the electrical circuitry raises the source terminal of the PMOS transistor to the intermediate voltage in response to a /WLEN line transition to digital “0.” Raising the source terminal to an intermediate voltage limits current loss through the PMOS transistor when a differential voltage develops between the gate and drain terminals of the PMOS transistor.
Electrical circuitry is also provided that raises the source terminal of the PMOS transistor to a full supply voltage after a differential voltage develops between the gate and drain terminals of the PMOS transistor. In one embodiment, the electrical circuitry raises the source terminal of the PMOS transistor to a full supply voltage in response to a /PSA line transition to digital “0.”
The electrical circuits of the invention activate a sense amplifier in less time and cause the sense amplifier to amplify a differential voltage between the gate and drain terminals of the PMOS transistor to a full digital logic separation in less time. Additionally, the electrical circuits of the invention result in more efficient power consumption by the sense amplifier.
Improved methods for driving a DRAM sense amplifier having low threshold voltage PMOS transistors are also provided in accordance with the invention.
DRAM circuits including sense amplifier driver circuitry of the invention and systems that incorporate the invention are further provided.
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Fish & Neave
Lebentritt Michael S.
Luu Pho M.
Snell Peter F.
Tuma Garry J.
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