Driver for tri-state bus

Details Driver for tri-state bus Driver for tri-state bus

1995-05-10

1997-07-08

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326 93, 326 28, 326 58, H03K 190185, H03K 1900

Patent

active

056465530

ABSTRACT:
A tri-state synchronous bus driver avoids contention between succeeding cycles by shutting off each device's output enable early, so that it is guaranteed to no longer drive the line by the time any other device begins to drive. Enable activation occurs on a leading edge of the bus clock, and deactivation occurs at a delayed half phase clock edge. A low current bus holding cell is coupled to each bi-directional line to maintain the driven signal value until it can be sampled by a receiving device. This has the advantages that set up time is not eroded by the technique, and that the disable timing is relatively non-critical. The technique is particularly useful in gate array technology as process, temperature, and voltage variation can cause considerable fluctuation in the actual timing of circuits.

REFERENCES:
patent: 4766334 (1988-08-01), Warner
patent: 5086427 (1992-02-01), Whittaker et al.
patent: 5115149 (1992-05-01), Hashimoto
patent: 5225723 (1993-07-01), Drako et al.
patent: 5251305 (1993-10-01), Murphy, Jr. et al.

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