Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1998-09-25
2001-02-20
Santamauro, Jon (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S037000
Reexamination Certificate
active
06191611
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to programmable logic devices, and more particularly to driver circuitry usable in programmable logic devices with increased logic and interconnection capability.
Programmable logic devices are well known as is shown, for example, by Pedersen et al. U.S. Pat. No. 5,260,610, Cliff et al. U.S. Pat. No. 5,260,611, Cliff et al. U.S. Pat. No. 5,689,195, Cliff U.S. Pat. No. 5,815,726, Cliff et al. U.S. Pat. No. 5,909,126 Reddy et al. U.S. Pat. No. 5,977,793, McClintock et al. U.S. Pat. No. 5,999,016, and Pedersen U.S. patent application Ser. No. 09/022,663, filed Feb. 12, 1998. All of these references are hereby incorporated by reference herein in their entirety.
Programmable logic devices can include a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such super-regions. Each super-region may include a plurality of regions of programmable logic. Each region may include a plurality of subregions of programmable logic. Each subregion may include (1) a four-input look-up table which is programmable to produce an output signal that is any logical combination of the four inputs applied to the look-up table, (2) a register (flip-flop) for registering the output signal of the look-up table, and (3) circuitry for allowing the final output of the subregion to be either the registered or unregistered output signal of the look-up table.
Interconnection conductors are provided on the device for conveying signals to, from, and between the subregions in each region, as well as to, from, and between the regions and super-regions. For example, horizontal interconnection conductors may be associated with each row of regions for conveying signals to, from, and between the regions in the associated row. Vertical interconnection conductors may be associated with each column of regions for conveying signals to, from, and between the rows. And local conductors may be associated with each region for conveying signals to, from, and between the subregions in that region. Programmable interconnections are provided for making connections between the various types of interconnection conductors so that signals can be routed throughout the device in a great many different ways. For example, the local conductors associated with each region may be programmably interconnectable to the horizontal and/or vertical conductors adjacent to that region. Similarly, intersecting horizontal and vertical conductors may be programmably interconnectable.
Various kinds of drivers may be provided for driving signals from the subregions out onto the adjacent interconnection conductors. For example, certain of the horizontal and vertical conductors adjacent to each region may be driven by the output signals of that region's subregions via a buffer and an NMOS pass gate. Each such buffer may be capable of driving one or more horizontal and/or vertical conductors. Each pass gate is controlled by an associated static programmable element. Alternative driver circuitry involves the use of tri-state drivers feeding tri-state lines. The enable signal for each tri-state buffer is generated elsewhere on the device or comes from an input pin. Thus each such enable signal must be explicitly routed to each tri-state driver that it controls. This can result in extra delay in the enable path and may require considerable routing resources.
In view of the foregoing, it is an object of this invention to provide improved driver circuitry for programmable logic devices.
It is a more particular object of this invention to provide improved tri-state-type driver circuitry for programmable logic devices.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing a new programmable logic device architecture with an improved logic array block (“LAB”) and improved interconnection resources. For interconnecting signals to and from the LABs, the global interconnection resources may include switch boxes, long lines, double lines, single lines, and half- and partially populated multiplexer regions. The LAB includes two levels of function blocks. In a preferred embodiment, in a first level, there are eight four-input function blocks. In a second level, there are two four-input function blocks. In another preferred embodiment there are 16 first-level and four second-level four-input function blocks. At least one tri-state buffer is provided. The tri-state buffer may be programmably coupled to receive signals from and send signals to the LABs without passing through the global interconnection resources. The tri-state buffer may also be programmably coupled to receive signals from and send signals to the global interconnection resources. In one embodiment, the function blocks are implemented using look-up tables (“LUTs”). The LAB may contain storage blocks for implementing sequential or registered logic functions.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
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Altera Corporation
Fish & Neave
Jackson Robert R.
Santamauro Jon
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