Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-06-29
2001-03-20
Nelms, David (Department: 2818)
Electronic digital logic circuitry
Interface
Current driving
C365S230060
Reexamination Certificate
active
06204692
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driver circuit unit, and more particularly to a driver circuit unit for issuing data to a transmission line.
2. Description of the Related Art
A so-called driver circuit unit functions to issue transmitted data having been received therein to a receiver through a transmission line. Inputted to the above driver circuit unit as input signals are: positive-phase data which is the above mentioned transmitted data having been received in the driver circuit unit; and, negative-phase data which is one reversed in phase of the positive-phase data. Further, issued from the above driver circuit unit to the receiver are: an output signal corresponding to the above positive-phase data; and, an negative-phase output signal corresponding to the above one reversed in phase of the positive-phase data. More specifically, as shown in
FIG. 4
, inputted to a conventional driver circuit
101
are: positive-phase data
201
which is the above-mentioned transmitted data and a negative-phase data
202
.
For example, as shown in
FIG. 5
, when the positive-phase data
201
is constructed of a series of signals with logic levels H and L, i.e., a series of signals with high level (H), high level (H), low level (L), high level (H), low level (L) and low level (L) sequentially arranged in a row in the above-mentioned order, the negative-phase data
202
is constructed of a series of the negative-phase ones of the signals with the above-mentioned logic levels. In other words, the negative-phase data
202
is constructed of a series of low level (L), low level (L), high level (H), low level (L), high level (H) and high level (H) sequentially arranged in a row in the above-mentioned order, as shown in FIG.
5
.
In operation, as shown in
FIG. 4
, when the conventional driver circuit
101
receives the positive-phase data
201
together with the negative-phase data
202
, a pair of switches
101
A,
101
B perform their switching operations in accordance with these two data
201
,
202
. In other words, in the driver circuit
101
, when the positive-phase data
201
is in the high level, a resistor
101
c
is connected with a power supply line(+). In contrast with this, when the positive-phase data
201
is in the low level, the resistor
101
C is connected to the ground. Further, in the driver circuit
101
, when the negative-phase data
202
is in the low level, a resistor
101
D is connected to the ground. In contrast with this, when the negative-phase data
202
is in the high level, the resistor
101
D is connected with the power supply line.
As a result, when the above-mentioned transmitted data is in the high level, the resistor
101
C has a voltage equal to that V
DD
of the power supply line, and the resistor
101
D is held at the ground level in voltage. On the other hand, when the transmitted data is in the low level, the resistor
101
C is connected to the ground, and the resistor
101
D is held at the voltage VDD of the power supply line.
The resistors
101
C and
101
D of the driver circuit
101
are connected with coaxial cables forming transmission lines
102
and
103
, respectively. At this time, in the driver circuit
101
, the positive-phase data
201
and the negative-phase data
202
are transmitted from the driver circuit
101
to the transmission lines
102
and
103
, respectively, provided that the resistors
101
C,
101
D are used to have the impedance of the driver circuit
101
matched to that of each of the transmission lines
102
and
103
.
In a receiver
104
shown in
FIG. 4
, a signal produced between a pair of the transmission lines
102
and
103
is received in a series circuit of a pair of resistors
104
A,
104
B. A node N interposed between the resistors
104
A,
104
B is connected to the ground through a capacitor
104
C. In operation, in the receiver
104
, when the above-mentioned transmitted data is in the high level, an electric current flows in the direction of the arrow
104
E through the series circuit of the resistors
104
A,
104
B. On the other hand, when the transmitted data is in the low level, the electric current flows in the direction of the arrow
104
F through the above series circuit of the resistors
104
A,
104
B. As a result, an input signal
211
is produced at a node “P” located between the resistor
104
A and the transmission line
102
. On the other hand, another input signal
212
is produced at a node “Q” located between the resistor
104
B and the transmission line
103
. The thus produced input signals
211
,
212
are inputted to a differential operation portion
104
D.
In this differential operation portion
104
D, the electric current flowing in the direction of the arrow
104
E produces a high level signal which is issued from the differential operation portion
104
D. Also in this differential operation portion
104
D, the electric current flowing in the direction of the arrow
104
F produces a low level signal which is also issued from the differential operation portion
104
D.
This differential operation portion
104
D is shown in FIG.
6
. The differential operation portion
104
D shown in
FIG. 6
is constructed of a two-stage circuit which is provided with both a differential amplifier
110
and an inverter
120
. As shown in
FIG. 6
, the differential amplifier
110
is constructed of: a plurality of P (i.e., Positive) type MOS (i.e., Metal Oxide Semiconductor) transistors
111
,
112
,
113
; and, a pair of N (i.e., Negative) type MOS transistors
114
,
115
. On the other hand, the inverter
120
is constructed of a P type MOS transistor
121
and an N type MOS transistor
122
.
Both the MOS transistors
112
,
113
of the differential amplifier
110
operate upon receipt of a constant electric current supplied from the MOS transistor
111
. Inputted to the MOS transistor
112
through an input terminal
131
is an input signal
211
generated at the node “P” shown in FIG.
4
. On the other hand, inputted to the other MOS transistor
113
through an input terminal
132
is an input signal
212
generated at the node “Q” shown in FIG.
4
.
In operation, when the input signal
211
inputted to the input terminal
131
is higher in level than the input signal inputted to the input terminal
132
(in other words, when the transmitted data mentioned above is in the high level), the MOS transistor
112
is turned OFF so as to be non-conductive, while the other MOS transistor
113
is turned ON so as to be conductive. Due to this, the constant electric current issued from the MOS transistor
111
is supplied, through the MOS transistor
113
, to the MOS transistor
115
which serves as a resistor, so that a node “R”, through which a drain of the MOS transistor
113
is connected with a drain of the MOS transistor
115
, becomes the high level. When this node “R” becomes the high level, the MOS transistor
114
is turned ON so as to be conductive, so that a node “S” through which a drain of the MOS transistor
114
is connected with a drain of the MOS transistor
112
becomes the low level.
When the node “S” becomes the low level, the MOS transistor
121
is turned ON so as to be conductive, while the MOS transistor
122
is turned OFF so as to be non-conductive. As a result, an output terminal
133
, which forms a node trough which a drain of the MOS transistor
121
is connected with a drain of the MOS transistor
122
, becomes the high level.
In contrast with this, when the input signal
211
inputted to the input terminal
131
is lower in level than the other input signal
212
inputted to the input terminal
132
(in other words, when the transmitted data described in the above is in the low level), the MOS transistor
112
is turned ON so as to be conductive, while the other MOS transistor
113
is turned OFF so as to be non-conductive . Since the MOS transistor
112
is turned ON so as to be conductive while the other MOS transistor
113
is turned OFF so as to be non-conductive as described above, the node “R” becomes the low level
NEC Corporation
Nelms David
Tran M.
Young & Thompson
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