Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-01-18
2003-12-30
Le, Don (Department: 2181)
Electronic digital logic circuitry
Interface
Current driving
C326S030000, C326S083000
Reexamination Certificate
active
06670830
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a signal transmission bus system for transmitting an electrical signal, such as a high-speed digital signal with a frequency of several gigahertz or more, over a transmission line from a driver circuit to a receiver circuit.
A conventional signal transmission bus system, depicted in
FIG. 21
, includes a transmission line
101
, a driver circuit
102
, and a receiver circuit
103
formed in or mounted on a circuit substrate
104
. In a typical application, the driver circuit
102
and receiver circuit
103
are disposed in separate integrated-circuit (IC) chips, which are mounted on the circuit substrate
104
. A power-supply pattern
105
and a ground pattern
106
are formed within the circuit substrate
104
. The power-supply pattern
105
supplies power from a power supply, generically denoted Vdd, to the driver circuit
102
, receiver circuit
103
, and other circuits. Although shown as a line in the drawing, the power-supply pattern
105
may occupy part or all of a plane in the circuit substrate
104
. A ground pattern
106
, likewise having a broad planar extent, connects the driver circuit
102
, receiver circuit
103
, and other circuits to the ground side of the power supply, denoted by the conventional ground symbol and the letters GND. The transmission line
101
is configured as a microstrip transmission line.
The driver circuit
102
and receiver circuit
103
are complementary metal-oxide-semiconductor (CMOS) circuits, each having a p-channel metal-oxide-semiconductor field-effect transistor (hereinafter, pMOS transistor) with its source electrode coupled to the power-supply pattern
105
, an n-channel metal-oxide-semiconductor field-effect transistor (hereinafter, nMOS transistor) with its source electrode coupled to the ground pattern
106
, an input terminal connected to the gate electrodes of these two transistors, and an output terminal connected to the drain electrodes of the two transistors. The two ends of the transmission line
101
are coupled to the output terminal of the driver circuit
102
and the input terminal of the receiver circuit
103
. The input impedance of the receiver circuit
103
exceeds the characteristic impedance of the transmission line
101
.
The driver circuit
102
receives a transmit input signal TS from an external source, and places a corresponding transmitted signal on the transmission line
101
. The receiver circuit
103
receives the transmitted signal and generates a corresponding receive output signal RS.
One advantage of a CMOS driver circuit such as the driver circuit
102
is its low power dissipation. Power dissipation is low because significant current flows only when the transmit input signal TS changes state.
A high-to-low transition of the transmit input signal TS causes current (denoted I
LH
) to flow from the power-supply pattern
105
through the pMOS transistor in the driver circuit
102
into the microstrip transmission line
101
. On the microstrip transmission line
101
, the transmitted signal propagates as an electromagnetic wave from the driver circuit
102
to the receiver circuit
103
, changing the potential level sensed by the receiver circuit
103
from low to high. In the power-supply pattern
105
, a flow of charge occurs as electrons drift from the driver circuit
102
toward the power supply Vdd. Repeated at each high-to-low transition of the transmit input signal TS, this flow of charge creates a current flow with an alternating (ac) component in the power-supply pattern
105
.
Similarly, a low-to-high transition of the transmit input signal TS causes current (denoted I
HL
) to flow from the microstrip transmission line
101
through the nMOS transistor in the driver circuit
102
into the ground pattern
106
. On the microstrip transmission line
101
, the transmitted signal again propagates as an electromagnetic wave from the driver circuit
102
to the receiver circuit
103
, changing the potential level sensed by the receiver circuit
103
from high to low. In the ground pattern
106
, a flow of charge occurs as electrons drift from ground toward the driver circuit
102
. Repeated at each low-to-high transition of the transmit input signal TS, this flow of charge creates a current flow with an ac component in the ground pattern
106
.
If, for example, the power-supply voltage Vdd is 3.3 volts, the transistors in the driver circuit
102
have on-resistances of fifteen ohms (15 &OHgr;) and off-resistances of one hundred thousand ohms (100 k&OHgr;), and the resistance of the transmission line
101
is one hundred ohms (100 &OHgr;), then the so-called dark current that flows from the power supply through the power-supply pattern
105
to the transmission line
101
when the transmission line
101
is at the low (ground) potential level, and from the transmission line
101
through the ground pattern
106
to ground when the transmission line
101
is at the high (Vdd) potential level, has the comparatively small value of three hundred thirty microamperes.
3.3 V/(100 &OHgr;+100 k&OHgr;)=330 &mgr;A
If the signal propagation time on the transmission line
101
is one nanosecond (1 ns), then during that one nanosecond, the current I
LH
or I
HL
flowing into or out of the microstrip transmission line
101
, charging or discharging the capacitance of the transmission line
101
, has the comparatively large value of twenty-nine milliamperes.
3.3 V/(15 &OHgr;+100 &OHgr;)=29 mA
If the transmit input signal TS is a high-speed digital signal with a frequency of several gigahertz (GHz), for example, then an alternating current component of comparable frequency, with a magnitude equal to the difference between the above two current values, is generated in the power-supply pattern
105
and ground pattern
106
. This comparatively large, high-frequency ac component can perturb the power-supply and ground potentials and affect the signal transmission bus system as a whole. Resonating with stray inductances and capacitances, it can cause the signal transmission bus system to malfunction.
Another problem is waveform distortion due to substantially total reflection of the transmitted signal at the receiver circuit
103
. If, for example, TS transitions occur at frequencies of several gigahertz and the signal propagation time on the transmission line
101
is one nanosecond, then each reflection may distort multiple pulse waveforms, which are propagating simultaneously in the transmission line
101
, and each waveform may be distorted by multiple reflections. The reflection distortions are further increased if the transmission line
101
is connected as a signal bus to multiple receiver circuits.
The above resonance effects and multiple reflection effects also generate electromagnetic radiation, which can give rise to eddy currents in extended planar areas of the power-supply pattern
105
and ground pattern
106
. The eddy currents in turn generate further electromagnetic radiation, which becomes electromagnetic interference (EMI) affecting other circuits on the circuit substrate
104
.
Another problem is that when the TS frequency is high enough to make the TS pulse width less than the signal propagation time (e.g., 1 ns) on the transmission line
101
, a large current (either I
LH
or I
HL
) flows almost continuously, so the CMOS advantage of low power dissipation is lost.
As a solution to the problems of the signal transmission bus system shown in
FIG. 21
, the present inventors have proposed the signal transmission bus system shown in
FIG. 22
(disclosed in Japanese Unexamined Patent Publication No. 10-348270). The transmission line in this system is a transmission line pair
201
comprising parallel signal transmission lines
201
a
,
201
b
of equal length, interconnected by a termination resistance
202
at one end, connected to a driver circuit
203
at the other end, and having one or more branching sections
204
(two are shown) at intermediate points between the two ends. The branching sections
204
coupl
Otsuka Kanji
Usami Tamotsu
Otsuka Kanji
Volentine & Francos, PLLC
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