Driver circuit having reduced noise

Details Driver circuit having reduced noise Driver circuit having reduced noise

1998-03-30

2000-07-04

Tokar, Michael

Electronic digital logic circuitry

Interface

Current driving

326 83, 326 86, 326 21, 326 26, 326 27, 326 29, 326 30, H03K 1716, H03K 19175

Patent

active

060844329

ABSTRACT:
A driver circuit has an output node coupled to a chip pad. A first PFET and a first resistor are connected between a power supply and the output node, wherein the first resistor is connected between the first PFET and the output node. A first NFET and a second resistor are connected between a ground potential and the output node, wherein the second resistor is connected between the first NFET and the output node. A third resistor is connected between an input to the driver circuit and a gate electrode of the first PFET. A fourth resistor is connected between the input to the driver circuit and a gate electrode of the first NFET. The pre-drive circuitry for driving the input to the PFET may include an NFET coupled between the ground potential and the input, wherein the gate electrode of the NFET receives the data signal to be driven. The NFET pre-drive circuitry may include a PFET coupled between the power supply and the input to the NFET portion of the driver circuit, wherein the gate electrode of this PFET also receives the data signal to be driven. A plurality of these driver circuits may be connected in parallel and in series in order to modify the output impedance.

REFERENCES:
patent: 4859877 (1989-08-01), Cooperman et al.
patent: 4952818 (1990-08-01), Erdelyi et al.
patent: 5089722 (1992-02-01), Amedeo
patent: 5448181 (1995-09-01), Chiang
patent: 5633600 (1997-05-01), Ohnishi
patent: 5699000 (1997-12-01), Ishikuri
patent: 5717343 (1998-02-01), Kwong
patent: 5801563 (1998-09-01), McClure

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