Driver circuit having programmable slew rate

Details Driver circuit having programmable slew rate Driver circuit having programmable slew rate

2008-05-27

2008-05-27

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S026000, C326S027000, C327S170000, C327S108000

Reexamination Certificate

active

07378878

ABSTRACT:
The programmable slew rate driver uses separate and programmably selectable resistors for time constants for on and off transitions on the NMOS and PMOS output transistors. By proper setting of gate voltage time constants and overlap of NMOS and PMOS “on” times, a desired output slew rate is accomplished, having a smooth output transition, without generation of shoot-through current. The programmable slew rate driver includes a first driver transistor coupled between the first supply voltage and output, a second driver transistor coupled between the second supply voltage and output, a plurality of upper transition blocks coupled in parallel and a plurality of lower transition blocks coupled in parallel between the first and second supply voltage. The rates of change and overlap of the gate voltages are in turn substantially determined by the resistance of the lower transition control blocks and the capacitance of the gate of the second driver transistor.

REFERENCES:
patent: 5568081 (1996-10-01), Lui et al.
patent: 6304120 (2001-10-01), Taito
patent: 6359484 (2002-03-01), Ajit
patent: 6441653 (2002-08-01), Spurlin
patent: 6559676 (2003-05-01), Tomita
patent: 6768363 (2004-07-01), Yoo et al.

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