Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Accelerating switching
Patent
1997-04-25
1998-08-04
Dinh, Son T.
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Accelerating switching
327108, 327112, 327437, 327478, H03K 19013
Patent
active
057899657
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to a driver circuit for driving a switching unit. This driver circuit is particularly suitable for use in switched-mode power supplies and for driving transistors in switched-mode converters. A driver circuit of this type is disclosed, for example, in 301 Analog IC Designs, Ferranti Interdesign, Inc., 1987, Page 113, Circuit Example 260. This circuit arrangement has the disadvantage that low-value input resistors cause a high current consumption. The known circuit arrangement furthermore has the disadvantage that the sink and source currents are too small for a relatively high switching frequency.
SUMMARY OF THE INVENTION
The invention is based on the object of specifying a driver circuit for high switching frequencies.
In general terms the present invention is a driver circuit having a first edge driver, which contains a first drive unit and a first switching-through unit, which has at least one first transistor. It is used for switching a first operating potential through to the output of the driver circuit. A second edge driver contains a second drive unit and a second switching-through unit, which has at least one second transistor. It is used for switching a second operating potential through to the output of the driver circuit. The emitter of the first transistor is connected to the collector of the second transistor and to an output of the driver circuit. The first drive unit is formed from an amplifier stage, which contains at least one first transistor, and from a downstream thyristor circuit. The second drive circuit is formed from a first and second emitter follower. The collector of the second emitter follower is connected to a collector of the first transistor of the first drive unit and, via a first diode, to the base of the first transistor. The collectors of the emitter followers are additionally connected via second and third diodes to the output of the driver circuit. The inputs of the first and second edge drivers are connected to one another via a resistor and are driven via one of the inputs.
Advantageous developments of the present invention are as follows. A partial circuit unit having a further transistor is provided. A capacitor, a diode and a resistor are connected to the base of the further transistor. The collector of the further transistor is connected to the base of the second transistor. The capacitor is connected to the collector of the second transistor. The emitter of the further transistor and the second terminal of the diode as well as the second terminal of the resistor are connected to the second operating potential.
The entire edge driver power of the second edge driver remains active during the active phase thereof.
A level converter stage is connected to the input of the second edge driver, the collector of the output transistor of the level converter stage having an open collector and being connected to the input of the second edge driver.
When an error message is present at the level converter stage, the second edge driver is activated and the first edge driver is deactivated.
In addition to the advantage that a fast high/low edge change is achieved, the invention affords the additional advantages that there is a small bias current requirement for operating the driver circuit and a charge stored at the output of the driver circuit is concomitantly used to drive the falling edge.
It is an advantageous development of the invention that the entire driver power remains active in the event of a potential corresponding to a low phase at the gate of the switching unit; this affords the advantage that, in the event of an inductive load, a current which decays over a relatively long period of time and is effective at the drain of the NMOS transistor via the parasitic drain-gate capacitance at the gate of the transistor, is discharged.
The provision of means for the charge reversal of parasitic capacitances at the nodes which are internal to the circuit and are connected to the circuit unit is an advantageous refinement
REFERENCES:
patent: 4251742 (1981-02-01), Beelitz
patent: 5258667 (1993-11-01), Ohtake et al.
patent: 5296760 (1994-03-01), Oertle et al.
patent: 5349243 (1994-09-01), McClure
patent: 5408136 (1995-04-01), Ovens et al.
patent: 5576654 (1996-11-01), Shu et al.
patent: 5587676 (1996-12-01), Chowdhury
301 Analog IC Designs, Ferranti Interdesign, Inc., 1987, p. 113.
Brakus Bogdan
Roth Heinz-Jurgen
Dinh Son T.
SGS-Thomson Microelectronics GmbH
Siemens Aktiengesellschaft
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