Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-05-06
2001-01-16
Nelms, David (Department: 2818)
Electronic digital logic circuitry
Interface
Current driving
C326S031000, C326S086000
Reexamination Certificate
active
06175252
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driver circuit suitable for use as an output stage of logic circuits formed in Large Scale Integrated Circuits (LSI).
2. Background Art
Some logic circuits formed in LSIs are provided with driver circuits for the purpose of driving a large capacitive load at the output stage.
FIG. 4
shows such a driver circuit
50
and an overview of the output side.
The driver circuit shown in
FIG. 4
is connected to the PMOS-Tr (P-channel Metal Oxide Semiconductor field effect Transistor)
52
and NMOS-Tr (N-channel Metal Oxide Semiconductor field effect Transistor)
53
, and the output end of the driver circuit is connected to the gate terminal of the PMOS-Tr
52
and the gate terminal of the NMOS-Tr
53
, and the driver circuit
50
is provided with an inverter
51
which is a pre-driver for driving the PMOS-Tr
52
and the NMOS-Tr
53
.
The output terminal
74
of the driver circuit
50
is connected with a logic circuit
62
having a gate
63
as an inputting stage for receiving the signals from the driver circuit
50
. This output terminal
74
is also to be connected to capacitive load
61
such as a floating capacity which is carried on a wiring to the logic circuit
62
and an input capacity of the gate
63
.
When an “H” (high voltage level) signal is input at the data input end
71
of the driver circuit
50
, the driver circuit
50
charges the large capacitive load
61
connected to the output terminal
74
of the driver circuit
50
. When, in contrast, the “L” (low voltage level) signal is input at the data input end
71
, the driver circuit
50
discharges the large capacitive load
61
.
However, problems arise in the driving circuit structure shown in
FIG. 4
as follows. The first problem is that the conventional driving circuit requires a high driving current and its operating speed is low, since the load capacity is fully oscillated in a voltage range corresponding to the driving voltage.
The second problem is the wide gate width, since it is required for the PMOS-Tr
52
and the NMOS-TR
53
to have the ability to output large electric currents. Consequently, it is likely that noise components will be carried on wiring to the electric source or wiring to the ground. The third problem is that the penetration current becomes large during load driving for the same reasons as described above.
It is therefore the object of the present invention to provide a driver circuit which does not require a high output current even if a logic circuit with a large capacitive component is connected as a load, and which is capable of high speed operation or of reduced noise.
SUMMARY OF THE INVENTION
According to the first aspect of the present invention, a driver circuit comprises: a first detecting means for detecting that a voltage level at the load side exceeds the first voltage level (VthH) existing between the source potential voltage level and the logic threshold voltage level of a logic gate located at the receiving side; a second detecting means for detecting that the voltage level at the load side is below the second voltage level (VthL) existing between a ground potential voltage level and said first voltage level; a first driving element for switching on/off of the connection between the electric source and the load based on an input voltage level and the detection results by said first detecting means; and a second driving element for switching on/off of the connection between the ground potential and the load based on the input voltage level and the detection result by said second detecting means.
According to the second aspect of the present invention, in a driver circuit according to the first aspect, said first detecting means comprises a logic gate having a high logic threshold value, and the logic gate being an inverter comprising a P-channel field effect transistor having a large ratio of gate width to gate length and an N-channel field effect transistor having a small ratio of gate width to gate length.
According to the third aspect of the present invention, in a driver circuit according to the first aspect, said first detecting means comprises a logic gate having a low logic threshold value, and said logic gate being an inverter comprising a P-channel field effect transistor having a small ratio of the gate width to the gate length and an N-channel field effect transistor having a large ratio of the gate width to the gate length.
According to the fourth aspect of the present invention, in a driver circuit according to the first aspect, when said input voltage level is at a high voltage level, said first driving means is maintained in the on state until it is detected that the voltage level of the load exceeds said first voltage level by said first detecting means; and, said first driving means is turned off when the voltage level of the load exceeds the first voltage level by said first detecting means.
According to the fifth aspect of the present invention, in a driver circuit according to the first aspect, when the input voltage level is at a low voltage level, said second driving means is maintained in the on state until it is detected that the voltage level of the load exceeds said second voltage level by the second detecting means; and said second driving means is turned off when the voltage level of the load exceeds the first voltage level by said second detecting means.
According to the sixth aspect of the present invention, a driver circuit comprises a first driving means to be turned on when the input voltage level is at a high voltage level; and a third driving means to be turned off when the voltage level of the load exceeds the first voltage level; wherein said first driving means and said third driving means are connected in series between the source voltage source and said load.
According to the seventh aspect of the present invention, a driver circuit comprises: a second driving means to be turning on when the input voltage level is at a high voltage level; and a fourth driving means to be turning off when the voltage level of the load is below the second voltage level; wherein said fourth driving means and said second driving means are connected in series between a ground potential and said load.
According to the eighth aspect of the present invention, in a driver circuit according to claim
1
, said first voltage level is higher than the logic threshold of the logic gate for receiving signals from the driver circuit and said first voltage level is a potential which makes the penetration current flowing in said logic gate to a sufficiently small level when said voltage level is input in the logic gate located at the receiving side.
According to the ninth aspect of the present invention, in a driver circuit according to claim
1
, said second voltage level is below the logic threshold of the logic gate at the receiving side for receiving signals from the driver circuit and said second voltage level corresponds to a voltage so as to reduce the penetration current flowing in said logic gate sufficiently small when said voltage level is input in the logic gate located at the receiving side.
According to the present invention, the first driving means for switching on or off a connection between the source voltage and the load, when the input voltage level is high, maintains the on state until the load voltage level exceeds the first voltage level by the first detecting means, and turns off when it is detected that the load voltage level is below the first voltage level. The second driving means for switching on/off between the ground potential and the load, when the input voltage level is low, maintains the on state until the second detecting means detects that the load voltage level is below the second voltage level, and turns off when the second detecting means detects that the load voltage level is below the second voltage level.
Furthermore, there are provided a first driving means and a third driving means connected in series between the source voltage and the load
Le Thong
NEC Corporation
Nelms David
Sughrue Mion Zinn Macpeak & Seas, PLLC
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