Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2003-04-10
2004-04-13
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S233100, C365S189080, C365S149000, C327S153000, C327S161000
Reexamination Certificate
active
06721214
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a drive circuit and a control method that may serve for driving a voltage generator in a dynamic random access memory (DRAM) for example.
In DRAMs, the voltage generators present in the DRAM are generally switched off in the standby mode in order to save power. To that end, on the DRAM there is a controller that uses a control signal to control the enable inputs of the voltage generators. The voltage generators have to be switched on again in the event of a change from the standby mode to the active mode. To that end, a specific minimum switch-on time duration is necessary until the voltage generators are ready for use again. In this case, the minimum switch-on time duration depends on the voltage generator itself. In the case of a voltage generator that requires a relatively long time duration in order to attain the active mode, frequent rapid changes between the standby and active modes can lead to oscillation of the voltage generator. This results in an uncontrolled behavior of the voltage generator because the switch-on operations cannot be completely ended.
Hitherto, when there has been the risk of oscillation, the problem has been solved by the active time of the voltage generators being lengthened without exception. In this case, no distinction has been made between required and unrequired lengthening of the switch-on duration.
German Patent DE 100 00 758 C2 discloses a pulse generator for DRAMs in which an input signal is put onto a signal output in a manner delayed by a defined minimum pulse duration, in order to ensure that an output pulse always has a defined minimum pulse duration.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a drive circuit and a control method that overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which oscillation of, for example, a voltage generator driven by the circuit is avoided and clearly defined states can thus be achieved for the voltage generator, the voltage generator is switched on completely and an unnecessary current consumption is avoided.
With the foregoing and other objects in view there is provided, in accordance with the invention, a drive circuit for controlling an operating mode change of a voltage generator in a memory component. The drive circuit contains a control signal input for receiving an activation signal or a deactivation signal for the voltage generator, a control signal output outputting a control output signal to the voltage generator, a delay element having an input and an output and generating a delay duration, and a control logic circuit connected to the control signal input, the control signal output and the delay element. The control logic circuit:
in an event of a signal change from the activation signal to the deactivation signal at the control signal input, switches through the deactivation signal to the control signal output directly if the delay duration prescribed by the delay element has been exceeded; and
in an event of a signal change from the activation signal to the deactivation signal at the control signal input, switches through the deactivation signal to the control signal output in a manner delayed by the delay duration prescribed by the delay element, if the delay duration has been undershot.
The solution according to the invention has the advantage that the average current consumption of the driven circuits (e.g. voltage generators) is reduced through the optimized switch-on time duration.
For this purpose, the drive circuit according to the invention has a control signal input and a control signal output, a delay element for generating a delay duration, and also a control logic circuit. The latter controls the delay element and switches a change in the state at the control signal input to the control signal output in a manner delayed by the delay element, if a minimum time interval between state changes at the control signal input is undershot.
In the case of the control method according to the invention, a delay element is driven by a control logic circuit having a control signal input and a control signal output, the delay element generating a delay duration. A change in the state at the control signal input is switched by the control logic circuit to the control signal output in a manner delayed by the delay element, if a minimum time interval between state changes at the control signal input is undershot.
In one embodiment of the circuit according to the invention, the control logic circuit switches a change in the state at the control signal input to the control signal output directly, if the minimum time interval between two state changes at the control signal input is exceeded.
It is advantageous if the delay duration is adjustable because this enables the circuit to be adapted to the specific requirements of the downstream device, for example of a voltage generator.
In one embodiment of the invention, the control logic circuit has a resettable store, whose set input is connected to the control signal input and whose reset input is connected to the output of the delay element and the control signal input. The output of the control logic circuit is connected to the input of the delay element and the control signal output.
In a further embodiment of the invention, the output of the delay element is combined with the control signal input by an AND gate.
It is advantageous to configure the resettable store as an RS flip-flop since the latter constitutes a simple and cost-effective embodiment.
The circuit according to the invention advantageously serves for controlling a voltage generator.
The circuit according to the invention can also be used in a memory component, in particular a DRAM.
The circuit according to the invention is suitable for being used in an integrated component.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a drive circuit and a control method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 6088255 (2000-07-01), Matsuzaki et al.
patent: 6101137 (2000-08-01), Roh
patent: 6476657 (2002-11-01), Kuhne
patent: 100 00 758 (2001-08-01), None
Hausmann Michael
Schnabel Joachim
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
Yoha Connie C.
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