DRAMs having on-chip row copy circuits for use in testing and vi

Details DRAMs having on-chip row copy circuits for use in testing and vi DRAMs having on-chip row copy circuits for use in testing and vi

1994-08-15

1995-08-08

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Complementing/balancing

36518908, 365195, 365201, G11C 700

Patent

active

054405173

ABSTRACT:
A DRAM integrated circuit device has a memory array with multiple row access lines, multiple paired digit lines that intersect the row access lines, and a plurality of memory cells coupled at the intersections to form rows of memory cells. The row access lines are used to access associated rows of memory cells and the paired digit lines are used to carry data to and from the access memory cells. An equilibrate control is coupled to the digit lines to erase data thereon. An on-chip row copy circuit is provided to copy data carried by the paired digit lines and stored in a first row of memory cells to at least one other row of memory cells by suspending activation of the equilibrate control to prevent erasure of the data on the paired digit lines.

REFERENCES:
patent: 5241500 (1993-08-01), Barth, Jr. et al.
patent: 5293340 (1994-03-01), Fujita
patent: 5315598 (1994-05-01), Tran
patent: 5355337 (1994-10-01), Kim

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