Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2001-03-16
2003-06-17
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S195000
Reexamination Certificate
active
06580650
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
A DC analog circuit is disclosed which monitors a dynamic random access memory (DRAM) sample cell access device, and outputs a DC reference voltage to a word line voltage regulation system. The resulting output voltage, V
pp
, from the word line voltage regulation system, will then vary in accordance with the cell access device parametrics to guarantee that a full high-level voltage will always be written into the DRAM cell.
2. Related Art
A typical DRAM must operate within the framework of the overall system timing and global bus scheduling. Therefore, the DRAM architecture as well as individual memory cell designs are closely tied to timing issues.
The global bus serves as both the address bus and the data bus. One consequence of this arrangement is that a read or write operation to the DRAM memory core takes exactly two system clock cycles. In the first, or address, cycle, the read/write memory address is presented on the global bus and is latched in by the address register on the DRAM chip. In the second, or data, cycle, the DRAM receives the write enable control bit and the write data (if any). During this second cycle, data is either written to, or read from, the memory core and subsequently presented on the global bus.
A refresh cycle, however, operates somewhat differently. During a refresh cycle, an internally generated row address selects a row in the memory to be refreshed. In column-wise parallel fashion, the (inverted) row data is read out, inverted by the refresh circuitry, and then written back into the same row. To ensure device reliability, the voltage level of this write back signal must be both of a sufficient amplitude and free of ripple or other induced noise. The column and row addresses may be either loaded separately, on sequential clock cycles, or they may be presented at the same time.
One problem faced by DRAM designers is to select a sample cell access device circuit
100
having a word line WL voltage, V
pp
, (
FIGS. 1A
,
1
B) that is adequately high to achieve a full writeback level in the cell when the cell access device is weak (i.e., there are a high threshold voltage (V
t
), a long channel, a narrow width, and a thicker oxide), while at the same time not exceeding the breakdown voltage of the dielectric material in the cell structure. One common solution is to fix the word line voltage V
pp
as high as possible near the reliability limits of the technology. In process cases where the cell access device is weak, this fixed voltage solution is inadequate. The cell writeback signal will fall short of its bitline “high” voltage (V
BLH
) goal, as illustrated in
FIG. 1B
by voltage curve
150
.
An improvement sought by many designers involves monitoring a sample cell access device and automatically adjusting the word line voltage, V
pp
, to a level which tracks the threshold fluctuations of the cell device, at a minimum, to insure that it is always conductive when the source is at bitline potential. Curve
160
in
FIG. 1B
illustrates this concept. The advantages of such an improved method would be a lower nominal word line voltage giving rise to better reliability and lower current consumption from the word line voltage regulation system.
Another approach that has been attempted in the related art is illustrated in
FIG. 2. A
diode-connected sample cell access device
280
is installed in the feedback path
270
of the V
pp
word line voltage system monitor
250
, as shown in FIG.
2
. This approach, however, has several disadvantages. First, the drain and source voltages of the sample cell access device
280
do not correspond to the actual operating drain and source voltages of the cell device
280
near the end of writeback of a “high” level. Also, the resistive divider formed by resistors
240
and
260
attenuates the sample cell access device
280
process fluctuations, thereby reducing compensation effectiveness. Yet another disadvantage arises because the sample cell access device
280
must operate at low microampere (e.g., approximately 1 to 5 &mgr;A) current levels in order to mimic the actual cell charging current. Microampere currents transform into an impedance level, of the combined device and resistive divider
240
,
260
, in the several hundred thousand ohms range. This high impedance, combined with unavoidable stray capacitance, slows the response time of the feedback loop
270
, in turn causing excessive overshoot of the V
pp
goal voltage before the charge pump
220
shuts off. This effect produces an unacceptably high ripple voltage on V
pp
.
An improved prior art method taught by Foss et al. (U.S. Pat. No. 5,267,201, incorporated herein by reference) utilizes the sample cell access NFET device
350
in the feedback loop in a different manner, as shown in FIG.
3
. PFET devices
360
and
370
comprise a current mirror connected between V
pp
and the drain of sample cell access device
350
to sense its current. The current mirror drives the drain of NFET device
380
operating in the linear region as a resistive load and outputs a voltage to drive the inverters
410
and
420
to produce a logic level inhibit signal for switching the oscillator
440
on and off. The Foss circuit realizes two advantages over the approach embodied by the circuit of FIG.
2
. First, the source of NFET device
350
is properly referenced to the bitline high voltage V
dd
(same as V
BLH
) as desired, and secondly, V
pp
must achieve a high enough voltage for current to flow in NFET device
350
before an inhibit signal can be generated.
Although Foss has taught improvements, the circuit (
FIG. 3
) still suffers drawbacks. One drawback is the sample device current variation with the drain voltage set by diode-connected PFET
360
which has its own parametric fluctuations unrelated to the memory cell device. Sensitivity to this effect will be significantly magnified in very short channel (i.e. approximately 0.15 microns) modern DRAM technologies compared to the technology of the Foss era. Also, current through NFET device
350
that triggers an inhibit signal compares to the strength of the linear region NFET device
380
. Again, parametric variations of NFET device
380
will also influence the V
pp
level unrelated to the cell device.
Increasing load current demand on the V
pp
regulation system of modern day synchronous DRAMs (SDRAMs) presents a tougher design challenge especially if decoupling capacitance is limited. Stronger charge pumps combined with limited decoupling capacitance require faster transient response from the V
pp
level monitor to suppress V
pp
ripple. Foss's approach still relies on a sample cell access device located in the feedback loop contrary to the fast transient response requirement.
SUMMARY OF THE INVENTION
The present invention discloses a circuit and method which overcome all of the related art disadvantages, while at the same time achieving more precise control of V
pp
and guaranteeing a full cell writeback level. This circuit overcomes the major loop response problem of the related art by avoidance of the sample memory cell access device in the feedback loop of the V
pp
regulation system. Instead the sample cell access device is operated in a circuit under steady state DC conditions and outputs a DC reference voltage that changes in accordance with the parametrics of the sample memory cell access transistor. This DC reference voltage then becomes the reference supplied to the V
pp
level monitor in the V
pp
voltage regulation system.
The present invention provides a method of biasing and monitoring a sample cell access device for regulating the word line selection voltage of a dynamic random access memory (DRAM) chip, said method comprising: providing a sample cell access device wherein said sample cell access device substantially tracks the process parametric fluctuations of any one of a plurality of memory cell access devices within the DRAM chip; forcing a constant DC current through said sample cell access device; providing a DC voltage equal to the bi
Ellis Wayne F.
Houghton Russell J.
Jacunski Mark D.
Maffitt Thomas M.
Tonti William R.
Capella Steven
International Business Machines - Corporation
Schmeiser Olsen & Watts
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