DRAM with very shallow trench isolation

Details DRAM with very shallow trench isolation DRAM with very shallow trench isolation

2006-04-25

2006-04-25

Huynh, Andy (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S302000, C257S303000, C257S304000, C257S305000

Reexamination Certificate

active

07034352

ABSTRACT:
The methods and structures of the present invention involve providing a vertical dynamic random access memory (DRAM) cell device comprising a buried strap which can be laterally constrained, thereby maintaining freedom from cross talk, even at 6F2 scaling, in the absence of adjacent Shallow Trench Isolation (STI). The methods and structures of the present invention involve the further recognition that the STI can therefore be vertically confined, freed of any need to extend down below the level of the buried strap. The reduction of the buried strap to 1F width and the concomitant reduction in the depth of the STI together permit a significantly reduced aspect ratio, permitting critically improved manufacturability.

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