DRAM with total self refresh and control circuit

Details DRAM with total self refresh and control circuit DRAM with total self refresh and control circuit

2002-06-18

2004-05-25

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S222000, C365S227000

Reexamination Certificate

active

06741515

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to dynamic random access memories (DRAMs) and, more particularly, to an improved technique for refreshing DRAM memory cells.
2. Prior Art
Data is stored in a DRAM memory storage cell using charge that is stored on a capacitor in each memory storage cell. The presence or absence of stored charge represents either a one or a zero bit in a memory cell. The stored charge leaks away through various leakage mechanisms, and over time, the data represented by the charge is lost unless the charge stored in the memory storage cell is periodically refreshed with a refresh circuit to restore the charge. Because of this leakage, a refresh operation is typically required every 64 milliseconds. The need for a periodic refresh operation affects both external interface functions and control functions of the DRAM. DRAMs are constructed such that whenever a row of a DRAM is addressed, the memory storage cells in that row are automatically refreshed, regardless of whether the row addressing is for a READ, A WRITE, or a REFRESH operation.
The timing signals for an asynchronous DRAM are not synchronized to a system clock. An asynchronous DRAM is provided with an external row address select (RAS) command signal and with an external column address select (CAS) signal. During normal operation of an asynchronous DRAM, a RAS signal occurs before a CAS signal. In order to perform a typical refresh operation in an asynchronous DRAM, a CAS signal occurs before a RAS signal.
The timing signals for a synchronous DRAM are synchronized to a system clock so that timing is better controlled and the DRAM can operate at higher speeds. In an synchronous DRAM, an address strobe signal is generated when an address signal level transition is detected in one or more address signal lines. The first part of the address is a row address and the second part of the address is a column address that is provided after one or more clock pulses. RAS and CAS signals are generated in a synchronous DRAM and used with an auto-refresh command to refresh the charge in the memory cells.
Alternatively, many types of conventional asynchronous and synchronous DRAMs are refreshed by being placed in a standby mode with an external command. In the standby mode, a memory cell refresh is performed internally and this type of refreshing is referred to as a “self refresh.”
Various prior art schemes have been disclosed for hiding an internal refresh operation in a DRAM. These types of prior art schemes generally add more complexity to a DRAM to obtain higher speeds and better performance, whereas low power and reductions of circuit complexity and circuit area are usually desired for a DRAM.
One such prior art scheme is disclosed in a U.S. Pat. No. 5,999,474, granted to Leung et al. The '474 apparatus uses an SRAM cache and an associated cache tag memory, where the SRAM cache has a storage capacity that is {fraction (1/64)}th of the storage capacity of the DRAM. The SRAM cache has two separate very wide 256-bit read and write data buses. One disadvantage of the disclosed '474 apparatus is the large amount of circuit area is required by the SRAM cache. Since SRAM cache cells typically use 9 to 10 times the area of a DRAM memory cell, the additional area required for '474 apparatus is close to 15% of the area used for the DRAM memory arrays. Another disadvantage of the disclosed '474 apparatus is the need for the two separate wide data buses that are used to write and to read a cache line. This makes power consumption for the disclosed '474 apparatus dependent on the cache hit profile, which can result in high peak power and in high sustained power for certain situations.
Another prior art scheme is disclosed in a U.S. Pat. No. 5,596,545, granted to Lin for a semiconductor device with internal self-refreshing. The '545 apparatus uses a comparator to detect when there is a conflict between a refresh operation and a write operation. The comparator consumes silicon area and power unnecessarily and provides no performance advantage.
Another such prior art scheme is disclosed in a U.S. Pat. No. 5,835,401, granted to Green et. al. that describes a circuit for hiding a refresh operation of DRAM cells in a memory device. The '401 apparatus uses a shift register to speed up the generation of the refresh address. The '401 apparatus also requires either an external CLK signal or an external CE* signal to control the refresh operation. The disadvantages of the '401 apparatus are the increased silicon area required for the shift register and the need for an external CLK or CE signal to initiate the refresh operation.
FIG. 1
illustrates a generic DRAM system
10
that is shown to illustrate refreshing of either an asynchronous DRAM or a synchronous DRAM. The generic DRAM system
10
includes a DRAM memory cell array, or block,
12
that is arranged as rows and columns of memory cells. While a single DRAM array
12
is shown, it is understood that in a conventional DRAM there are typically several arrays of DRAM memory cells and these arrays are arranged as a set of several banks of memory cells. Individual rows of the DRAM array
12
are selected with a corresponding wordline, or row select, signal that is provided on one of a plurality of wordlines that are provided in a wordline bus
14
. The wordline signals are provided from a decoder/wordline driver circuit
16
that is activated by a decoder control signal on a control line
18
. Multi-bit address signals are inputted on a multi-line bus
20
to the decoder/wordline driver circuit
16
from a two-input multiplexer circuit
22
. The two-input multiplexer circuit
22
selects external address signals from a multi-line memory address bus
24
or internal address signals on a multi-line bus
26
from a multi-bit refresh counter
28
. Selection of the output of the multiplexer
22
is controlled by a multiplexer control signal that is provided on a control line
30
.
The DRAM array
12
is enabled with an array enable signal that is provided on a signal line
32
. A sense amplifier/read-write circuit
34
for data in and out of the DRAM array
12
is controlled by a memory read-write control signal on a control line
36
. For reading out data stored in one of the memory cells in the array
12
, the sense amplifier is used to detect the charge level in that memory cells to provide an output data bit on an I/O bus
38
. For writing data into one of the memory cells, input data is read into the memory cells of the array
12
from the I/O bus
38
.
A RAS control and memory timing circuit
40
provides the decoder control signal on control line
18
. The RAS control and memory timing circuit
40
provides the array enable signal on the signal line
32
. The RAS control and memory timing circuit
40
also provides the memory read-write control signal on the control line
36
.
For both asynchronous and synchronous types of DRAMS, an external RAS signal is provided at a RAS input terminal
42
. The RAS input terminal
42
is connected to an input terminal of a refresh command decode circuit
44
and is also connected to one input terminal of a two-input multiplexer
46
. For normal memory-access operations of the memory array
12
, that is, for read or write operations, the RAS signal is passed through the two-input multiplexer
46
to a signal line
48
that is connected to an input terminal of the RAS control and memory timing circuit
40
. This RAS signal produces appropriate control signals on control line
18
,
32
, and
36
, as previously mentioned.
For an asynchronous DRAM, an external CAS signal is provided at a CAS input terminal
50
of the refresh command decode circuit
44
. For a synchronous DRAM, an external AUTO REFRESH signal is also provided at an AUTO REFRESH input terminal
52
of the refresh command decode circuit
44
. During a normal memory-access operation of an asynchronous DRAM, a RAS signal is presented to input terminal
42
before a CAS signal is presented to CAS input

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