DRAM with super self-refresh and error correction for...

Details DRAM with super self-refresh and error correction for... DRAM with super self-refresh and error correction for...

2007-05-08

2007-05-08

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C714S014000, C714S042000

Reexamination Certificate

active

10699223

ABSTRACT:
In a semiconductor integrated circuit device, a command decoder is adapted to receive not only an external command but also an internal command. An ECC controller has a command generator and an address generator. When the command decoder decodes an external entry command, the command generator instructs encoding to an ECC-CODEC circuit and the address generator sequentially produces addresses which are supplied to a memory array. The ECC-CODEC circuit produces check bits for error detection/correction with reference to information data of the memory array. Upon completion of an encoding operation of writing the check bits into a predetermined region of the memory array, the ECC controller delivers an end signal to the command decoder as the internal command to make a super self-refresh control circuit start a super self-refresh operation.

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patent: 2004/0243886 (2004-12-01), Klein
patent: 362078920 (1987-04-01), None

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